Implement-a-CPU
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3045KB
下载次数：7
上传日期：2017-05-02 14:34:33
上 传 者：
Mick
说明： 在FPGA赛灵思基础3上使用Verilog HDL实现支持MIPS操作子集的CPU
(Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3)
文件列表:
ALU.v (5334, 2016-09-03)
BranchControl.v (2893, 2016-09-03)
EX.v (3526, 2016-09-03)
EX_MEM.v (1928, 2016-09-03)
ForwardControl.v (3279, 2016-09-03)
HazardControl.v (886, 2016-09-03)
ID.v (1295, 2016-09-03)
ID_EX.v (3968, 2016-09-03)
IF.v (707, 2016-09-03)
IF_ID.v (413, 2016-09-03)
LICENSE (16725, 2016-09-03)
MEM.v (1513, 2016-09-03)
MEM_WB.v (1372, 2016-09-03)
RM_ctrl.v (1270, 2016-09-03)
WM_ctrl.v (523, 2016-09-03)
decoder.v (12084, 2016-09-03)
define.v (3095, 2016-09-03)
doc (0, 2016-09-03)
doc\Five-Stage MIPS Pipeline in Verilog HDL.pdf (202717, 2016-09-03)
doc\Five-Stage MIPS Pipeline in Verilog HDL.tex (15965, 2016-09-03)
doc\Instructions.pdf (35602, 2016-09-03)
doc\blueprint.pdf (72011, 2016-09-03)
doc\branch.png (94903, 2016-09-03)
doc\cpu.bib (1368, 2016-09-03)
hilo_reg.v (906, 2016-09-03)
pipeline_CPU.v (11250, 2016-09-03)
regfile.v (3254, 2016-09-03)
testBenches (0, 2016-09-03)
testBenches\IF_tb.v (1006, 2016-09-03)
testBenches\SOPC.v (1857, 2016-09-03)
testBenches\dffe_tb.v (465, 2016-09-03)
testBenches\hilo_reg_tb.v (774, 2016-09-03)
testBenches\memory.v (2209, 2016-09-03)
testBenches\memory_tb.v (1947, 2016-09-03)
testBenches\mux2x1_tb.v (407, 2016-09-03)
testBenches\mux4x1_tb.v (586, 2016-09-03)
testBenches\regfile_tb.v (1888, 2016-09-03)
... ...
# MIPS_CPU
Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
## TODOs
1. [x] finish construction
* [x] `decoder.v`
* [x] `BranchControl.v`
* [x] `HazardControl.v`
* [x] `RM_ctrl.v`
* [x] `WM_ctrl.v`
* [x] solve div function
2. [x] fully review the pipeline code
3. test
* [x] write virtual memory, rom
* test on instrctions
* [x] ori
* [x] arithmetic operations
* [x] memory store/load
* [x] logic operations
* [x] bitwise operations
* [x] hi/lo operations
* [x] dependency test (forwarding)
* [x] jump operations
* [ ] overall test
4. improvement
* add cache
* implememt CP0
5. synthesis
6. write report
* clearly outline the supported instructions
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