文件列表:

_config.yml (25, 2017-05-06)
constraints (0, 2017-05-06)
constraints\pong_game.xdc (4630, 2017-05-06)
sources (0, 2017-05-06)
sources\ip (0, 2017-05-06)
sources\ip\clk_wiz_0.xcix (81561, 2017-05-06)
sources\new (0, 2017-05-06)
sources\new\SevenSegment.sv (2807, 2017-05-06)
sources\new\anim_gen.sv (11985, 2017-05-06)
sources\new\main_control.sv (2573, 2017-05-06)
sources\new\vga.sv (5389, 2017-05-06)

# BASYS 3 Board - Pong Game [](https://youtu.be/r8tnSQvCtVk) Our project is a two-player pong game created on BASYS-3 using the VGA output of the BASYS3. Project is coded in System Verilog and VHDL using VIVADO IDE. Top player controls are the up and down button on the boad and bottom player uses the left and right buttons and middle button is used to start the round. Current Scores are displayed on the seven segment display of the Basys board.  References: * The clk_wiz_0 block is provided by Xilinx. Instead of using a clock counter to be more precise we used Vivados own clk API clk_wiz_0. https://www.xilinx.com/products/intellectual-property/clocking_wizard.html * Sync_mod block is translated from another source, originally it was VHDL, it has translated into System Verilog. Original source code is from Jan Bukowski of http://mikrokontroler.pl/

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