ultrasonic
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：4906KB
下载次数：7
上传日期：2017-05-12 23:25:33
上 传 者：
何以解优
说明： 基于xilinx的超声波测距代码，通过了modelsim的仿真实现
(Based on xilinx ultrasonic distance code, through the modelsim simulation to achieve)
文件列表:
ultrasonic\cs_test.cdc (650, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.asy (193, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.constraints\chipscope_icon.ucf (375, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.constraints\chipscope_icon.xdc (793, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.gise (1282, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.ncf (375, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.ngc (31991, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.ucf (375, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.v (892, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.veo (1083, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.xco (1666, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.xdc (793, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon.xise (41072, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon_flist.txt (397, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_icon_xmdf.tcl (3321, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.asy (352, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.cdc (2268, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.constraints\chipscope_ila.ucf (440, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.constraints\chipscope_ila.xdc (477, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.gise (1279, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.ncf (384, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.ngc (351079, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.ucf (440, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.v (945, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.veo (1138, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.xco (4391, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.xdc (477, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila.xise (41061, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila_flist.txt (418, 2017-05-12)
ultrasonic\ipcore_dir\chipscope_ila_xmdf.tcl (3301, 2017-05-12)
ultrasonic\ipcore_dir\test.cgc (62799, 2017-05-12)
ultrasonic\ipcore_dir\test.cgp (521, 2017-05-12)
ultrasonic\ipcore_dir\tmp\_xmsgs\pn_parser.xmsgs (788, 2017-05-12)
ultrasonic\ipcore_dir\_xmsgs\xst.xmsgs (30210, 2017-05-12)
ultrasonic\iseconfig\ultrasonic.projectmgr (10126, 2017-05-12)
ultrasonic\iseconfig\ultrasonic.xreport (20369, 2017-05-12)
ultrasonic\modelsim.ini (82916, 2017-04-29)
ultrasonic\pa.fromHdl.tcl (664, 2017-05-12)
... ...
The following files were generated for 'chipscope_ila' in directory
H:\FPGA_DAIMA\TEST\xiaoche\ultrasonic\ipcore_dir\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_ila.cdc
* chipscope_ila.constraints/chipscope_ila.ucf
* chipscope_ila.constraints/chipscope_ila.xdc
* chipscope_ila.ncf
* chipscope_ila.ngc
* chipscope_ila.ucf
* chipscope_ila.v
* chipscope_ila.veo
* chipscope_ila.xdc
* chipscope_ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_ila.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* chipscope_ila.gise
* chipscope_ila.xise
Deliver Readme:
Readme file for the IP.
* chipscope_ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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