IIR-FPGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：16341KB
下载次数：34
上传日期：2017-05-24 11:08:15
上 传 者：
浮华丶
说明： 基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现
(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)
文件列表:
IIR滤波器FPGA程序\introduce.txt (102, 2006-11-10)
IIR滤波器FPGA程序\pro\coregen_xil_1808_64.cgc (2073, 2011-04-18)
IIR滤波器FPGA程序\pro\coregen_xil_1808_64.cgp (518, 2011-04-18)
IIR滤波器FPGA程序\pro\fuse.log (3584, 2011-04-18)
IIR滤波器FPGA程序\pro\iir.bgn (6650, 2012-03-31)
IIR滤波器FPGA程序\pro\iir.bit (464302, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.bld (1115, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.cmd_log (1625, 2012-03-31)
IIR滤波器FPGA程序\pro\iir.drc (177, 2012-03-31)
IIR滤波器FPGA程序\pro\iir.gise (16377, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.lso (6, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.ncd (92738, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.ngc (48216, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.ngd (376890, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.ngr (38856, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.pad (12162, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.par (8218, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.pcf (216, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.prj (61, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.ptwx (17226, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.stx (0, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.syr (17870, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.twr (5716, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.twx (24882, 2012-03-31)
IIR滤波器FPGA程序\pro\iir.ucf (0, 2011-04-18)
IIR滤波器FPGA程序\pro\IIR.unroutes (154, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.ut (552, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.v (2342, 2011-04-27)
IIR滤波器FPGA程序\pro\iir.xise (40051, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.xpi (46, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR.xst (1094, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_bitgen.xwbt (255, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_envsettings.html (12327, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_guide.ncd (92738, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_map.map (6876, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_map.mrp (129860, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_map.ncd (53010, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_map.ngm (582963, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_map.xrpt (29860, 2012-03-31)
IIR滤波器FPGA程序\pro\IIR_ngdbuild.xrpt (7043, 2012-03-31)
... ...
The following files were generated for 'multiply' in directory
D:\V3FPGA\LX45_BOARD\advanced\S18_IIR\pro\ipcore_dir\
multiply.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
multiply.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
multiply.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
multiply.sym:
Please see the core data sheet.
multiply.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
multiply.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
multiply.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
multiply.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
multiply.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
multiply.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
multiply_readme.txt:
Text file indicating the files generated and how they are used.
multiply_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
multiply_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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