shiyan2
所属分类：VHDL/FPGA/Verilog
开发工具：Proteus
文件大小：1302KB
下载次数：2
上传日期：2017-05-24 11:56:58
上 传 者：
hehe1995
说明： Verilog HDL实现十进制计数器,FPGA ISE开发环境
(
Verilog HDL decimal counter)
文件列表:
shiyan2 (0, 2017-04-14)
shiyan2\.Xil (0, 2017-04-14)
shiyan2\LED_Ten.bld (931, 2016-10-16)
shiyan2\LED_Ten.cmd_log (1350, 2016-10-16)
shiyan2\LED_Ten.lso (6, 2016-10-16)
shiyan2\LED_Ten.ncd (4922, 2016-10-16)
shiyan2\LED_Ten.ngc (3180, 2016-10-16)
shiyan2\LED_Ten.ngd (5294, 2016-10-16)
shiyan2\LED_Ten.ngr (2022, 2016-10-16)
shiyan2\LED_Ten.par (5095, 2016-10-16)
shiyan2\LED_Ten.pcf (221, 2016-10-16)
shiyan2\LED_Ten.prj (26, 2016-10-16)
shiyan2\LED_Ten.stx (0, 2016-10-16)
shiyan2\LED_Ten.syr (10115, 2016-10-16)
shiyan2\LED_Ten.twr (3606, 2016-10-16)
shiyan2\LED_Ten.twx (22009, 2016-10-16)
shiyan2\LED_Ten.unroutes (161, 2016-10-16)
shiyan2\LED_Ten.ut (393, 2016-10-16)
shiyan2\LED_Ten.v (1325, 2016-10-16)
shiyan2\LED_Ten.xst (1143, 2016-10-16)
shiyan2\LED_Ten_bitgen.xwbt (191, 2016-10-16)
shiyan2\LED_Ten_envsettings.html (15532, 2017-04-09)
shiyan2\LED_Ten_guide.ncd (4922, 2016-10-16)
shiyan2\LED_Ten_map.map (2289, 2016-10-16)
shiyan2\LED_Ten_map.mrp (6569, 2016-10-16)
shiyan2\LED_Ten_map.ncd (3450, 2016-10-16)
shiyan2\LED_Ten_map.ngm (10184, 2016-10-16)
shiyan2\LED_Ten_pad.csv (9648, 2016-10-16)
shiyan2\LED_Ten_pad.txt (41571, 2016-10-16)
shiyan2\LED_Ten_summary.html (7676, 2017-04-09)
shiyan2\LED_Ten_xst.xrpt (10822, 2016-10-16)
shiyan2\LED_test.v (1237, 2016-10-16)
shiyan2\LED_test_beh.prj (115, 2017-04-11)
shiyan2\LED_test_isim_beh.exe (94720, 2017-04-11)
shiyan2\LED_test_isim_beh.wdb (5130, 2017-04-11)
shiyan2\LED_test_isim_beh1.wdb (5122, 2016-10-16)
shiyan2\_ngo (0, 2017-04-14)
shiyan2\_ngo\cnt10_LED_cs_signalbrowser.ngo (29496, 2017-04-11)
shiyan2\_ngo\cnt10_LED_cs_signalbrowser.ver (20, 2017-04-11)
shiyan2\_ngo\cs_icon_pro (0, 2017-04-11)
... ...
The following files were generated for 'icon_pro' in directory
G:\Study\FPGA\shiyan2\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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