文件列表:

FPGA数字信号处理实现原理及方法 (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\dsp48e_application (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\dsp48e_application\accumulator_96bit_tb.vhd (2437, 2007-11-02)
FPGA数字信号处理实现原理及方法\dsp48e_application\addaccum96.v (5740, 2007-03-05)
FPGA数字信号处理实现原理及方法\dsp48e_application\addaccum96.vhd (10689, 2007-03-05)
FPGA数字信号处理实现原理及方法\dsp48e_application\mult59x59.v (30481, 2007-01-29)
FPGA数字信号处理实现原理及方法\dsp48e_application\mult59x59.vhd (34093, 2007-03-01)
FPGA数字信号处理实现原理及方法\dsp48e_application\mult59x59_tb.v (4929, 2007-02-27)
FPGA数字信号处理实现原理及方法\dsp48e_application\PolyDecFilter.zip (17409, 2005-08-19)
FPGA数字信号处理实现原理及方法\dsp48e_application\PolyIntrpFilter.zip (14553, 2005-08-19)
FPGA数字信号处理实现原理及方法\dsp48e_application\test (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\abs24_test.v (715, 2006-04-11)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\accum48_test.v (801, 2006-04-14)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\add4_46_test.v (912, 2006-04-18)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\addsub48_test.v (818, 2006-04-12)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\addsub96_test.v (627, 2006-05-04)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\autoreset_pd_test.v (822, 2006-05-04)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\barrelshifter_18bit_test.v (863, 2007-01-24)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\cntr_load_test.v (802, 2006-04-12)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\comp_mult_pipe_test.v (1108, 2006-05-04)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\conv_round_cc_test.v (680, 2006-05-11)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\conv_round_lsb_test.v (1330, 2006-05-18)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\div_mult_cascade_test.v (777, 2006-05-05)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\dsp_adder12_test.v (1456, 2006-04-12)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\dsp_adder24_test.v (940, 2006-04-14)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\dsp_adder48_test.v (702, 2006-04-14)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\fast_sqrt_mult_cascade_test.v (553, 2006-05-10)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\logic48_test.v (668, 2006-05-05)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\macc18x18_test.v (819, 2006-05-09)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\mult25x18_parallel_pipe_test.v (716, 2006-04-18)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\mult25x35_parallel_pipe_test.v (736, 2006-05-09)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\mult35x35_parallel_pipe_test.v (794, 2006-05-30)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\mult35x35_sequential_pipe_test.v (753, 2006-05-11)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\mult_low_power_test.v (709, 2006-06-08)
FPGA数字信号处理实现原理及方法\dsp48e_application\test\pattern_match_test.v (694, 2006-04-14)
FPGA数字信号处理实现原理及方法\dsp48e_application\ucf (0, 2011-03-30)
FPGA数字信号处理实现原理及方法\dsp48e_application\ucf\abs24.ucf (82, 2004-06-14)
FPGA数字信号处理实现原理及方法\dsp48e_application\ucf\accum48.ucf (82, 2004-06-14)
FPGA数字信号处理实现原理及方法\dsp48e_application\ucf\add4_46.ucf (82, 2004-06-14)
... ...

********************************************************************** ** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement,or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrantor ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits,cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright (c) 2003 Xilinx, Inc. ** All rights reserved ** ****************************************************************************** Revision Note July 12, 2005. Updated Fully Pipelined 35x35 Multiplier codes. The codes are mult35x35_parallel_pipe.v mult35x35_parallel_pipe.vhd August 05, 2005. Updated HDL files for the counter. Set CEC, CECTRL, CECINSUB to 1. Corrected OPMODE and ADD_SUB definition according to the counter section description in Chapter 2 August 11, 2005. Updated HDL files for accum48, mult35x18_sequential_pipe, and mult35x35_sequential_pipe. Corrected LEGACY attribute to mult18x18 when MREG is 0 November 27, 2005. Added div_sub_cascade.* files. January 30, 2006. Remeoved SIM_X_INPUT attribute from the VHDL and Verilog files. March 10, 2006. Registered OPMODE and SUBTRACT inputs of the DSP48 in the cntr_load.v and cntr_load.vhd files. May26, 2006. Changed the attribute passing statements in the Verilog codes. Fixed functional error in fast_sqrt_mult_cascade files. January 27, 2007 Changed the Barrelshifter code to include 17 bit shifting. This was done by using the SUBTRACT input. ****************************************************************************** basic math function zip (ug073_c02.zip) file contains Loadable counter design cntr_load.v cntr_load.vhd cntr_load.ucf Division using multiplier (DSP48 connected in cascaded mode) div_mult_cascade.v div_mult_cascade.vhd div_mult_cascade.ucf Division using subtrater (DSP48 connected in cascaded mode) div_sub_cascade.v div_sub_cascade.vhd div_sub_cascade.ucf Square root using multiplier (DSP48 connected in cascaded mode) sqrt_mult_cascade.v sqrt_mult_cascade.vhd sqrt_mult_cascade.ucf The verilog and vhdl synthesized and places and routed using Foundation 6.2.03i, Application version G-31. XST ws used for synthesis. All other synthesis and PAR settings were set to default.

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