reconf. router code xylinx
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2366KB
下载次数：14
上传日期：2017-06-05 20:24:23
上 传 者：
GIRISH
说明： design and fpga implementation of Routing algorithm for NOC
文件列表:
reconf. router code xylinx\east_input_fifo.v (2239, 2012-05-13)
reconf. router code xylinx\NOOPUR FINAL.ppt (2755584, 2012-09-10)
reconf. router code xylinx\north_input_fifo.v (2237, 2012-05-13)
reconf. router code xylinx\Reconfig Router Code (0, 2014-01-24)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code (0, 2014-01-24)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\core.ucf (390, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\core.v (1993, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\east_input_fifo.v (2200, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\north_input_fifo.v (2198, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\south_input_fifo.v (2199, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\tb_top_router.v (524, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\top_router.v (2544, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Reconfig_Hardware_code\west_input_fifo.v (2200, 2012-05-20)
reconf. router code xylinx\Reconfig Router Code\Simulation_code (0, 2014-01-24)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\east_input_fifo.v (2239, 2012-05-13)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\north_input_fifo.v (2237, 2012-05-13)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\south_input_fifo.v (2238, 2012-05-13)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\tb_top_router.v (1664, 2012-09-08)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\tb_top_router.v.bak (1668, 2012-09-08)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\top_router.v (2443, 2012-05-13)
reconf. router code xylinx\Reconfig Router Code\Simulation_code\west_input_fifo.v (2239, 2012-05-13)
reconf. router code xylinx\south_input_fifo.v (2238, 2012-05-13)
reconf. router code xylinx\tb_top_router.v (1668, 2012-05-13)
reconf. router code xylinx\top_router.v (2578, 2012-05-19)
reconf. router code xylinx\transcript (440, 2012-05-19)
reconf. router code xylinx\west_input_fifo.v (2239, 2012-05-13)
output
sel == 0000 -----> data_out = 00001011(11)
sel == 0001 -----> data_out = 00001011(11)
sel == 0010 -----> data_out = 00001011(11)
sel == 0011 -----> data_out = 00001011(11)
sel == 0100 -----> data_out = 00010110(22)
sel == 0101 -----> data_out = 00010110(22)
sel == 0110 -----> data_out = 00010110(22)
sel == 0111 -----> data_out = 00010110(22)
sel == 1000 -----> data_out = 00100001(33)
sel == 1001 -----> data_out = 00010110(22)
sel == 1010 -----> data_out = 00010110(22)
sel == 1011 -----> data_out = 00010110(22)
sel == 1100 -----> data_out = 00101100(44)
sel == 1101 -----> data_out = 00101100(44)
sel == 1110 -----> data_out = 00010110(22)
sel == 1111 -----> data_out = 00010110(22)
Hence north side uses 4 buffer(11)
south side uses 9 buffer(22)
east side uses 1 buffer(33)
west side uses 2 buffer(44)
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