文件列表:

bin (0, 2016-10-25)
bin\nexys4_fft_demo.bit (3825900, 2016-10-25)
proj (0, 2016-10-25)
src (0, 2016-10-25)
src\bd (0, 2016-10-25)
src\bd\fft_mag (0, 2016-10-25)
src\bd\fft_mag\fft_mag.bd (38729, 2016-10-25)
src\constraints (0, 2016-10-25)
src\constraints\Nexys4DDR_Master.xdc (17965, 2016-10-25)
src\hdl (0, 2016-10-25)
src\hdl\bram_to_fft.v (2195, 2016-10-25)
src\hdl\histogram.v (1005, 2016-10-25)
src\hdl\nexys4_fft_demo.v (10621, 2016-10-25)
src\hdl\oversampler.v (2049, 2016-10-25)
src\hdl\utils.v (6261, 2016-10-25)
src\ip (0, 2016-10-25)
src\ip\bram_fft (0, 2016-10-25)
src\ip\bram_fft\bram_fft.xci (23886, 2016-10-25)
src\ip\bram_frame (0, 2016-10-25)
src\ip\bram_frame\bram_frame.xci (23974, 2016-10-25)
src\ip\clk_wiz_0 (0, 2016-10-25)
src\ip\clk_wiz_0\clk_wiz_0.xci (75910, 2016-10-25)
src\ip\xadc_demo (0, 2016-10-25)
src\ip\xadc_demo\xadc_demo.xci (36499, 2016-10-25)

# Nexys 4 FFT Demo A simple Verilog example of a 4096pt FFT on analog input from a Nexys 4 XADC. The input is sampled at 1MSPS, oversampled to produce 14-bit samples at 62.5kHz, then sent to the FFT processing modules and passed through to PWM Audio out. The FFT outputs the magnitude for each frequency bin and a histogram of the frequency spectrum is output over VGA video ## Requirements ### Hardware * A Nexys 4 FPGA * Assorted resistors to attenuate and bias the analog input properly before going into the JXADC header on the Nexys 4. (+0.5V bias, 1Vpp) ### Software * Vivado 2016.2 or later for Nexys 4 development. ### Peripherals * A VGA monitor to display the FFT results ## Organization There are 3 folders * `bin` contains the latest working bitstream file that can be directly programmed onto a Nexys 4 * `proj` is intended to contain the Vivado project files, to keep them separate from the source. * `src` contains the actual sources in several folders for constraints, hdl, ip configuration, and block designs. These are fairly self-explanatory and are the core of the project. ## Setting up the project The procedure is roughly as follows: 1. Create a new Vivado project in the proj directory. 2. In the new project dialog: 1. Add all the hdl in src/hdl to the project 2. Add all the ips in src/ip to the project 3. Add the .xdc constraints file to the project 5. Once in the full IDE, click Add Sources again, specify Block Design, and add the fft_mag.bd block design in `src/bd` 8. Cross your fingers and synthesize/implement/write bitstream ## Shortcut 1. If you just want to see it working, just program from the saved bitfile in the `bin` folder

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