Connected Component Analysis-Labeling
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：37319KB
下载次数：42
上传日期：2017-06-19 17:47:57
上 传 者：
5546269
说明： 别人写的物体连通域计算的verilog 源代码
(Object connected domain calculation of the Verilog source code)
文件列表:
Connected Component Analysis-Labeling (0, 2017-05-12)
Connected Component Analysis-Labeling\ShapeR1.gise (17960, 2017-05-12)
Connected Component Analysis-Labeling\ShapeR1.xise (42865, 2017-05-10)
Connected Component Analysis-Labeling\Source (0, 2017-05-09)
Connected Component Analysis-Labeling\Source\0Top.v (10977, 2015-10-12)
Connected Component Analysis-Labeling\Source\1Defines.v (862, 2015-10-14)
Connected Component Analysis-Labeling\Source\BiaoJi.v (7199, 2015-10-12)
Connected Component Analysis-Labeling\Source\BigRam.v (6406, 2014-01-03)
Connected Component Analysis-Labeling\Source\CONS.ucf (4571, 2013-12-20)
Connected Component Analysis-Labeling\Source\ErZhi_TongJi.v (2723, 2015-10-12)
Connected Component Analysis-Labeling\Source\FuShiRam.v (11399, 2015-10-12)
Connected Component Analysis-Labeling\Source\HangRam.v (16036, 2015-10-12)
Connected Component Analysis-Labeling\Source\InOutBuffer.v (5977, 2015-10-12)
Connected Component Analysis-Labeling\Source\PanDuan.v (3635, 2014-01-03)
Connected Component Analysis-Labeling\Source\QuBian.v (3759, 2013-12-23)
Connected Component Analysis-Labeling\Source\QuZao.v (2615, 2014-01-09)
Connected Component Analysis-Labeling\Source\SaoMiao.v (25820, 2015-10-14)
Connected Component Analysis-Labeling\Source\ShiZhang.v (2287, 2014-01-09)
Connected Component Analysis-Labeling\Source\SuanZi9.v (5218, 2014-04-24)
Connected Component Analysis-Labeling\Source\TestBench (0, 2017-05-09)
Connected Component Analysis-Labeling\Source\TestBench\tb_Top.v (15070, 2015-10-14)
Connected Component Analysis-Labeling\Source\TongJiSuanFa.v (10758, 2017-05-10)
Connected Component Analysis-Labeling\Top.bld (1347, 2017-05-11)
Connected Component Analysis-Labeling\Top.cmd_log (1240, 2017-05-11)
Connected Component Analysis-Labeling\Top.lso (6, 2017-05-11)
Connected Component Analysis-Labeling\Top.ncd (1798740, 2017-05-11)
Connected Component Analysis-Labeling\Top.ngc (1492983, 2017-05-11)
Connected Component Analysis-Labeling\Top.ngd (4104491, 2017-05-11)
Connected Component Analysis-Labeling\Top.ngr (2453420, 2017-05-11)
Connected Component Analysis-Labeling\Top.pad (21390, 2017-05-11)
Connected Component Analysis-Labeling\Top.par (20004, 2017-05-11)
Connected Component Analysis-Labeling\Top.pcf (94147, 2017-05-11)
Connected Component Analysis-Labeling\Top.prj (698, 2017-05-11)
Connected Component Analysis-Labeling\Top.ptwx (17144, 2017-05-11)
Connected Component Analysis-Labeling\Top.stx (0, 2017-05-11)
Connected Component Analysis-Labeling\Top.syr (242116, 2017-05-11)
Connected Component Analysis-Labeling\Top.twr (72386, 2017-05-11)
Connected Component Analysis-Labeling\Top.twx (97876, 2017-05-11)
Connected Component Analysis-Labeling\Top.unroutes (4130, 2017-05-11)
Connected Component Analysis-Labeling\Top.xpi (46, 2017-05-11)
... ...
The following files were generated for 'VIO' in directory
F:\AnjlCaofan\FPGA\ShapeR1\ipcore_dir\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* VIO.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* VIO.cdc
* VIO.constraints/VIO.ucf
* VIO.constraints/VIO.xdc
* VIO.ngc
* VIO.ucf
* VIO.v
* VIO.veo
* VIO.xdc
* VIO_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* VIO.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* VIO.sym
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* VIO.gise
* VIO.xise
* _xmsgs/pn_parser.xmsgs
Deliver Readme:
Readme file for the IP.
* VIO_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* VIO_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：