VGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2087KB
下载次数：42
上传日期：2011-04-20 09:40:11
上 传 者：
messikou
说明： 用于vga显示，和图像的旋转，本程序部分可用作VGA接口，在此基础上惊醒图形在FPGA中的存储，显示和旋转。
(For vga display, and image rotation, this program can be used as part of the VGA interface and graphics on this basis, awakened in the FPGA, storage, display and rotate.)
文件列表:
VGA0\.untf (0, 2011-03-12)
VGA0\automake.log (0, 2011-04-09)
VGA0\bitgen.ut (601, 2011-04-09)
VGA0\core.tpl (5612, 2011-03-12)
VGA0\cos.coe (2967, 2011-03-12)
VGA0\cos_rom.asy (359, 2011-03-12)
VGA0\cos_rom.edn (35705, 2011-03-12)
VGA0\cos_rom.mif (6840, 2011-03-12)
VGA0\cos_rom.ngo (10473, 2011-03-12)
VGA0\cos_rom.sym (566, 2011-03-12)
VGA0\cos_rom.v (4164, 2011-03-12)
VGA0\cos_rom.veo (2963, 2011-03-12)
VGA0\cos_rom.vhd (4396, 2011-03-12)
VGA0\cos_rom.vho (3545, 2011-03-12)
VGA0\cos_rom.xco (1384, 2011-03-12)
VGA0\cos_rom_flist.txt (172, 2011-03-12)
VGA0\datarom.asy (359, 2011-03-12)
VGA0\datarom.edn (421298, 2011-03-12)
VGA0\datarom.mif (480000, 2011-03-12)
VGA0\datarom.ngo (179299, 2011-03-12)
VGA0\datarom.sym (566, 2011-03-12)
VGA0\datarom.v (4167, 2011-03-12)
VGA0\datarom.veo (2963, 2011-03-12)
VGA0\datarom.vhd (4399, 2011-03-12)
VGA0\datarom.vho (3545, 2011-03-12)
VGA0\datarom.xco (1394, 2011-03-12)
VGA0\datarom_flist.txt (172, 2011-03-12)
VGA0\Data_buf_reg.v (640, 2011-03-26)
VGA0\data_buf_reg.vhd (1066, 2011-03-26)
VGA0\dcm_25.vhd (5982, 2011-03-18)
VGA0\dcm_25.xaw (3918, 2011-03-18)
VGA0\dcm_25_arwz.ucf (841, 2011-03-18)
VGA0\desktop.ini (106, 2011-04-20)
VGA0\kou.coe (74, 2011-03-05)
VGA0\kou.coe_index.TXT (8, 2011-02-26)
VGA0\kou.TXT (115, 2011-02-26)
VGA0\kou.TXT_index.TXT (8, 2011-02-26)
VGA0\kou_index.TXT (8, 2011-02-25)
... ...
The following files were generated for 'cos_rom' in directory
D:\VHDL test Project\VGA:
cos_rom.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
cos_rom.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
cos_rom.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
cos_rom.sym:
Please see the core data sheet.
cos_rom.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
cos_rom.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
cos_rom.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
cos_rom.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
cos_rom.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
cos_rom_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
cos_rom_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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