E7_2_IntBitSync
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1126KB
下载次数：1
上传日期：2017-06-28 22:10:11
上 传 者：
lionsde
说明： 位同步的VHDL实现，代码可综合。很好用！
(Bit synchronization of the VHDL implementation, the code can be integrated. very useful!)
文件列表:
E7_2_IntBitSync\automake.log (0, 2013-03-18)
E7_2_IntBitSync\bitsync.bld (783, 2013-03-18)
E7_2_IntBitSync\bitsync.cmd_log (536, 2013-03-18)
E7_2_IntBitSync\BitSync.dhp (12348, 2013-03-18)
E7_2_IntBitSync\bitsync.edn (38189, 2013-03-18)
E7_2_IntBitSync\bitsync.fse (0, 2013-03-18)
E7_2_IntBitSync\BitSync.ise_ISE_Backup (4799, 2013-03-18)
E7_2_IntBitSync\bitsync.log (267, 2013-03-18)
E7_2_IntBitSync\bitsync.mrp (8065, 2013-03-18)
E7_2_IntBitSync\bitsync.ncd (12290, 2013-03-18)
E7_2_IntBitSync\bitsync.ncf (246, 2013-03-18)
E7_2_IntBitSync\bitsync.ngd (20363, 2013-03-18)
E7_2_IntBitSync\bitsync.ngm (36415, 2013-03-18)
E7_2_IntBitSync\bitsync.pad (9372, 2013-03-18)
E7_2_IntBitSync\bitsync.par (3391, 2013-03-18)
E7_2_IntBitSync\bitsync.par_nlf (1092, 2013-03-18)
E7_2_IntBitSync\bitsync.pcf (320, 2013-03-18)
E7_2_IntBitSync\bitsync.prj (1888, 2013-03-18)
E7_2_IntBitSync\bitsync.sdc (0, 2013-03-18)
E7_2_IntBitSync\bitsync.srd (16722, 2013-03-18)
E7_2_IntBitSync\bitsync.srm (21238, 2013-03-18)
E7_2_IntBitSync\bitsync.srr (9864, 2013-03-18)
E7_2_IntBitSync\bitsync.srs (7862, 2013-03-18)
E7_2_IntBitSync\bitsync.twr (3217, 2013-03-18)
E7_2_IntBitSync\bitsync.twx (16287, 2013-03-18)
E7_2_IntBitSync\BitSync.vhd (4641, 2013-03-18)
E7_2_IntBitSync\BitSync.vtc (1885, 2013-03-18)
E7_2_IntBitSync\bitsync.xpi (46, 2013-03-18)
E7_2_IntBitSync\bitsync_compile.tcl (18, 2013-03-18)
E7_2_IntBitSync\bitsync_map.ncd (7930, 2013-03-18)
E7_2_IntBitSync\bitsync_map.ngm (36415, 2013-03-18)
E7_2_IntBitSync\bitsync_map.tcl (14, 2013-03-18)
E7_2_IntBitSync\bitsync_pad.csv (9404, 2013-03-18)
E7_2_IntBitSync\bitsync_pad.txt (41801, 2013-03-18)
E7_2_IntBitSync\bitsync_summary.html (4527, 2013-03-18)
E7_2_IntBitSync\bitsync_timesim.nlf (1092, 2013-03-18)
E7_2_IntBitSync\bitsync_timesim.sdf (45733, 2013-03-18)
E7_2_IntBitSync\bitsync_timesim.vhd (42434, 2013-03-18)
E7_2_IntBitSync\clktrans.fse (0, 2013-03-18)
E7_2_IntBitSync\clktrans.ncf (246, 2013-03-18)
... ...
The following files were generated for in directory
D:\SyncPrograms\Chapter_7\E7_1_BitSync\BitSync:
sin.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
sin.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
sin.sym:
Please see the core data sheet.
sin.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
sin.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
sin.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
sin.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
sin.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
sin_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
sin_readme.txt:
Text file indicating the files generated and how they are used.
sin_SINCOS_TABLE_TRIG_ROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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