文件列表:

niosii-triple-speed-ethernet-4sgx230-qsys-141 (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\global_reset_generator.v (3646, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\qsys_tserd_4sgx230.qsys (97434, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\qsys_tserd_4sgx230.sopcinfo (1205282, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\board_diag (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\board_diag\create-this-app (3012, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\count_binary (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\count_binary\create-this-app (3024, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_alt_main (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_alt_main\create-this-app (3036, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_ucosii (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_ucosii\create-this-app (3033, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_world (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_world\create-this-app (3018, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_world_small (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\hello_world_small\create-this-app (3118, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\memtest (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\memtest\create-this-app (2994, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\memtest_small (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\memtest_small\create-this-app (3165, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\simple_socket_server_tse (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\simple_socket_server_tse\create-this-app (3145, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\web_server_tse (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\app\web_server_tse\create-this-app (3488, 2014-12-23)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\bsp (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\bsp\hal_default (0, 2015-01-13)
niosii-triple-speed-ethernet-4sgx230-qsys-141\software_examples\bsp\hal_default\create-this-bsp (723, 2014-12-23)
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readme - Triple Speed Ethernet Design Overview: ========= This design is provided to showcase the design example running on the Nios development boards and highlights many of the advanced features of the Nios II processor, Triple Speed Ethernet and the Scatter Gather DMA. Contents of the System: ======================= - Nios II/f Core - JTAG Debug Module (Level 1) - DDR SDRAM Controller (128MB) - CFI Flash Memory Interface (***MB) - Descriptor memories (On Chip Memory) - JTAG UART - UART (RS-232) - Two Timers - Ethernet Interface - LED PIO - Push Button PIO - Performance Counter - System ID Peripheral - PLLs Supported Software Examples: ============================ - Blank Project - Hello World - Board Diagnostic - Count Binary - Hello Free-Standing - Hello MicroC/OS II - Hello World Small - Memory Test - Simple Sockets Server * - Web Server * - The 3c120 development kit board is using RGMII interface for the PHY connection, the TSE initialization need to updated to turn on the timing control on the Marvell PHY. Please refer to the simple_socket_server_tse_3c120_rgmii and web_server_tse_3c120_rgmii for the details. Further Notes: ============== - The top level of this design is the HDL file generated around the Qsys Editor design. This wrapper performs the following functions: 1.) Renaming the DDR-associated pins from Qsys Editor to match the timing assignments produced by the DDR megafunction. 2.) If you modify and regenerate the Qsys Editor design, the port list of the Qsys Editor instance may change. You must manually edit the HDL wrapper file to rectify any discrepancies. - This Quartus II project contains assignments that match the port names produced by Qsys Editor. If you add or modify Qsys Editor components, the pin assignments may no longer be valid. To view the Assignment Editor in the Quartus II software, in the Assignments menu, click "Assignment Editor". - This design contains the DDR memory and Triple Speed Ethernet components. Any design containing these cores must be re-generated in Qsys Editor before re-compiling it in Quartus if the installation path to the Altera toolchain has changed since it was last generated. This is because these cores make use of RTL libraries that are referenced using absolute paths. The re-generation process will update these absolute paths. Attempting to recompile in Quartus II without regenerating will result in an error of the following form during Quartus II Analysis and Synthesis: Error: Node instance "ddr_control" instantiates undefined entity "auk_ddr_controller" - Only single bank DDR memory is used as program and data memory. Thus, memtest should not run on the DDR memory bank as could cause destructive effect to the program code and data. - The current version of the Nios II EDS hardware design example uses an HDL file as the top level of the design hierarchy. If you would like to use a schematic-based top level instead (BDF), follow the steps listed below. 1) In the Quartus II software, open the top-level HDL file (.v or .vhd) for the design. 2) Create a symbol for the HDL file by clicking File -> Create/Update -> Create Symbol Files for Current File 3) Create a new BDF file by clicking File -> New -> Block Diagram/Schematic File. 4) Instantiate the symbol in the BDF by double-clicking in the empty space of the BDF file and selecting "Project -> " 5) Instantiate pins in the BDF by double-clicking empty space, then typing "input", "output", or "bidir". 6) Rename the pins and connect them to the appropriate ports on the symbol. 7) Save the BDF as a unique filename. 8) Set the BDF as your top level entity by clicking: Project -> Set as Top-Level Entity 9) Recompile the Quartus II project. - This example design should be used with any of the Altera's Partner Development Board Daughter Cards (http://www.altera.com/products/devkits/kit-daughter_boards.jsp) listed below: 1) 10/100 Ethernet PHY Daughter Card with National Semiconductor PHY (http://www.morethanip.com/boards_10_100_dp83848.htm) 2) 10/100/1000 Ethernet PHY Daughter Board with Marvell PHY (http://www.morethanip.com/boards_10_100_1000_88E1111.htm) 3) 10/100/1000 Ethernet PHY Daughter Card with National Semiconductor PHY (http://www.morethanip.com/boards_10_100_1000_dp83865.htm) - For more information, please refer to http://www.altera.com/support/examples/nios2/exm-nios2.html

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