dpll
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：427KB
下载次数：27
上传日期：2011-04-21 10:16:45
上 传 者：
wuxiuquan
说明： 本工程为锁相环，采用全数字系统设计，输出频率在10M~100M之间！可改进。
(This project is phase-locked loop, all-digital system design, the output frequency between the 10M ~ 100M! Can be improved.)
文件列表:
dpll (0, 2010-09-07)
dpll\db (0, 2010-09-08)
dpll\db\add_sub_1sh.tdf (2433, 2010-09-02)
dpll\db\add_sub_2sh.tdf (2590, 2010-09-02)
dpll\db\add_sub_5sh.tdf (3061, 2010-09-04)
dpll\db\add_sub_6sh.tdf (3219, 2010-09-04)
dpll\db\add_sub_lth.tdf (4577, 2010-09-02)
dpll\db\add_sub_mth.tdf (4748, 2010-09-02)
dpll\db\dpll.(0).cnf.cdb (1369, 2010-09-04)
dpll\db\dpll.(0).cnf.hdb (1129, 2010-09-04)
dpll\db\dpll.(1).cnf.cdb (2023, 2010-09-02)
dpll\db\dpll.(1).cnf.hdb (695, 2010-09-02)
dpll\db\dpll.(2).cnf.cdb (798, 2010-09-02)
dpll\db\dpll.(2).cnf.hdb (514, 2010-09-02)
dpll\db\dpll.(3).cnf.cdb (1227, 2010-09-02)
dpll\db\dpll.(3).cnf.hdb (765, 2010-09-02)
dpll\db\dpll.(4).cnf.cdb (3476, 2010-09-04)
dpll\db\dpll.(4).cnf.hdb (854, 2010-09-04)
dpll\db\dpll.asm.qmsg (1773, 2010-09-04)
dpll\db\dpll.cbx.xml (842, 2010-09-06)
dpll\db\dpll.cmp.bpm (660, 2010-09-04)
dpll\db\dpll.cmp.cdb (19981, 2010-09-04)
dpll\db\dpll.cmp.ecobp (28, 2010-09-04)
dpll\db\dpll.cmp.hdb (9309, 2010-09-04)
dpll\db\dpll.cmp.logdb (4, 2010-09-04)
dpll\db\dpll.cmp.rdb (29298, 2010-09-04)
dpll\db\dpll.cmp.tdb (16220, 2010-09-04)
dpll\db\dpll.cmp0.ddb (53249, 2010-09-04)
dpll\db\dpll.cmp_bb.cdb (9406, 2010-09-04)
dpll\db\dpll.cmp_bb.hdb (9053, 2010-09-04)
dpll\db\dpll.cmp_bb.logdb (4, 2010-09-04)
dpll\db\dpll.cmp_bb.rcf (5055, 2010-09-04)
dpll\db\dpll.dbp (0, 2010-09-06)
dpll\db\dpll.db_info (135, 2010-09-02)
dpll\db\dpll.eco.cdb (160, 2010-09-08)
dpll\db\dpll.eds_overflow (3, 2010-09-07)
dpll\db\dpll.fit.qmsg (36036, 2010-09-04)
dpll\db\dpll.fnsim.cdb (10506, 2010-09-06)
dpll\db\dpll.fnsim.hdb (27629, 2010-09-06)
dpll\db\dpll.fnsim.qmsg (40876, 2010-09-06)
... ...
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