design-IR-Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：9827KB
下载次数：2
上传日期：2017-07-15 11:00:53
上 传 者：
神通广大
说明： IR传感器使用Verilog语言编程，平台实在FPGA Cycle 4上实现
(IR sensor using Verilog programming language, the platform is really FPGA Cycle 4 implementation)
文件列表:
design-IR-Verilog\beep.v (577, 2013-10-07)
design-IR-Verilog\db\altsyncram_2r14.tdf (6412, 2014-02-13)
design-IR-Verilog\db\altsyncram_4r14.tdf (7487, 2014-02-13)
design-IR-Verilog\db\beep.map_bb.logdb (4, 2013-10-06)
design-IR-Verilog\db\beep.smp_dump.txt (297, 2013-10-06)
design-IR-Verilog\db\cmpr_ngc.tdf (1687, 2014-02-13)
design-IR-Verilog\db\cmpr_qgc.tdf (1919, 2014-02-13)
design-IR-Verilog\db\cntr_23j.tdf (3301, 2014-02-13)
design-IR-Verilog\db\cntr_egi.tdf (3736, 2014-02-13)
design-IR-Verilog\db\cntr_i6j.tdf (3569, 2014-02-13)
design-IR-Verilog\db\decode_dvf.tdf (1568, 2014-02-13)
design-IR-Verilog\db\dt.map_bb.logdb (4, 2013-10-07)
design-IR-Verilog\db\dt.smp_dump.txt (297, 2013-10-07)
design-IR-Verilog\db\IR.map_bb.logdb (4, 2014-02-28)
design-IR-Verilog\db\IR.smp_dump.txt (582, 2014-02-28)
design-IR-Verilog\db\key.map_bb.logdb (4, 2013-10-07)
design-IR-Verilog\db\key.smp_dump.txt (297, 2013-10-07)
design-IR-Verilog\db\led.map_bb.logdb (4, 2013-10-06)
design-IR-Verilog\db\led.smp_dump.txt (279, 2013-10-06)
design-IR-Verilog\db\logic_util_heursitic.dat (52140, 2014-02-28)
design-IR-Verilog\db\mux_ssc.tdf (3544, 2014-02-13)
design-IR-Verilog\db\prev_cmp_beep.qmsg (4713, 2013-10-06)
design-IR-Verilog\db\prev_cmp_dt.qmsg (7211, 2013-10-07)
design-IR-Verilog\db\prev_cmp_IR.qmsg (127714, 2014-02-28)
design-IR-Verilog\db\prev_cmp_key.qmsg (8134, 2013-10-07)
design-IR-Verilog\db\prev_cmp_led.qmsg (121231, 2013-10-06)
design-IR-Verilog\db\top.(0).cnf.cdb (4753, 2014-02-13)
design-IR-Verilog\db\top.(0).cnf.hdb (2379, 2014-02-13)
design-IR-Verilog\db\top.(1).cnf.cdb (4574, 2014-02-13)
design-IR-Verilog\db\top.(1).cnf.hdb (1133, 2014-02-13)
design-IR-Verilog\db\top.(10).cnf.cdb (1532, 2014-02-13)
design-IR-Verilog\db\top.(10).cnf.hdb (1308, 2014-02-13)
design-IR-Verilog\db\top.(11).cnf.cdb (1622, 2014-02-13)
design-IR-Verilog\db\top.(11).cnf.hdb (660, 2014-02-13)
design-IR-Verilog\db\top.(12).cnf.cdb (1053, 2014-02-13)
design-IR-Verilog\db\top.(12).cnf.hdb (1053, 2014-02-13)
design-IR-Verilog\db\top.(13).cnf.cdb (1450, 2014-02-13)
design-IR-Verilog\db\top.(13).cnf.hdb (783, 2014-02-13)
design-IR-Verilog\db\top.(14).cnf.cdb (1053, 2014-02-13)
design-IR-Verilog\db\top.(14).cnf.hdb (1053, 2014-02-13)
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