文件列表:

XAUI\Bitstreams (0, 2011-06-16)
XAUI\Bitstreams\ispvm.xcf (3269, 2009-06-12)
XAUI\Bitstreams\xaui_demo.bit (2408966, 2011-06-01)
XAUI\Bitstreams\xaui_demo.pad (65677, 2011-06-01)
XAUI\Bitstreams\xaui_demo.twr (57859, 2011-06-01)
XAUI\Docs (0, 2011-06-16)
XAUI\Docs\UG23.pdf (1204724, 2011-09-14)
XAUI\ORCAstra Plug-ins (0, 2011-06-16)
XAUI\ORCAstra Plug-ins\8000 (0, 2011-06-16)
XAUI\ORCAstra Plug-ins\8000\EyeDemo.vbs (4676, 2009-06-08)
XAUI\ORCAstra Plug-ins\8000\EyeDemo.vis (34566, 2009-06-08)
XAUI\ORCAstra Plug-ins\8000\EyeDemo_imgX(1).bmp (14046, 2009-03-16)
XAUI\ORCAstra Plug-ins\8000\EyeDemo_J(1).bmp (822, 2009-03-16)
XAUI\Sim (0, 2011-06-16)
XAUI\Sim\Src (0, 2011-06-16)
XAUI\Sim\Src\aaa_xaui_tb.v (21593, 2009-03-19)
XAUI\Src (0, 2011-06-16)
XAUI\Src\IPExpress (0, 2011-06-16)
XAUI\Src\IPExpress\CJPAT.lpc (717, 2009-06-08)
XAUI\Src\IPExpress\CJPAT.srp (1291, 2009-06-08)
XAUI\Src\IPExpress\CJPAT.v (22810, 2009-06-08)
XAUI\Src\IPExpress\CJPAT_generate.log (1479, 2009-06-08)
XAUI\Src\IPExpress\CJPAT_tmpl.v (257, 2009-06-08)
XAUI\Src\IPExpress\CRPAT.lpc (717, 2009-06-08)
XAUI\Src\IPExpress\CRPAT.srp (1291, 2009-06-08)
XAUI\Src\IPExpress\CRPAT.v (22810, 2009-06-08)
XAUI\Src\IPExpress\CRPAT_generate.log (1479, 2009-06-08)
XAUI\Src\IPExpress\CRPAT_tmpl.v (257, 2009-06-08)
XAUI\Src\IPExpress\msg_file.log (1355, 2009-06-08)
XAUI\Src\IPExpress\SCCJPATX4.mem (4494, 2009-01-15)
XAUI\Src\IPExpress\SCCRPATX4.mem (4329, 2009-01-15)
XAUI\Src\IPExpress\tb_CJPAT_tmpl.v (932, 2009-06-08)
XAUI\Src\IPExpress\tb_CRPAT_tmpl.v (932, 2009-06-08)
XAUI\Src\IPExpress\Xaui_0.lpc (4512, 2010-04-06)
XAUI\Src\IPExpress\Xaui_0.naf (4914, 2010-04-06)
XAUI\Src\IPExpress\Xaui_0.pp (5998, 2010-04-06)
XAUI\Src\IPExpress\xaui_0.sym (5262, 2010-04-06)
XAUI\Src\IPExpress\Xaui_0.tft (3452, 2010-04-06)
XAUI\Src\IPExpress\Xaui_0.txt (5444, 2010-04-06)
... ...

TOOL: orcapp DATE: 19-MAR-2008 13:11:52 TITLE: Lattice Semiconductor Corporation MODULE: Xaui_0 DESIGN: Xaui_0 FILENAME: Xaui_0.readme PROJECT: Unknown VERSION: 2.0 This file is auto generated by the ispLEVER NOTE: This readme file has been provided to instantiate the interface netlist. Since this template contains synthesis attributes for precision that are crucial to the design flow, we recommend that you use this template in your FPGA design. `timescale 1ns/ 1 ps module chip ( // Add your FPGA design top level I/Os here // ASIC side pins for PCSD. These pins must exist for the // PCS core. hdinp_ch0, hdinn_ch0, hdoutp_ch0, hdoutn_ch0, hdinp_ch1, hdinn_ch1, hdoutp_ch1, hdoutn_ch1, hdinp_ch2, hdinn_ch2, hdoutp_ch2, hdoutn_ch2, hdinp_ch3, hdinn_ch3, hdoutp_ch3, hdoutn_ch3, refclkp, refclkn, // Add FPGA side pins of PCS here ); // This defines all the high-speed ports. You may have to remove // some of them depending on your design. input hdinp_ch0; // exemplar attribute hdinp_ch0 NOPAD true input hdinn_ch0; // exemplar attribute hdinn_ch0 NOPAD true input hdinp_ch1; // exemplar attribute hdinp_ch1 NOPAD true input hdinn_ch1; // exemplar attribute hdinn_ch1 NOPAD true input hdinp_ch2; // exemplar attribute hdinp_ch2 NOPAD true input hdinn_ch2; // exemplar attribute hdinn_ch2 NOPAD true input hdinp_ch3; // exemplar attribute hdinp_ch3 NOPAD true input hdinn_ch3; // exemplar attribute hdinn_ch3 NOPAD true input refclkp; // exemplar attribute refclkp NOPAD true input refclkn; // exemplar attribute refclkn NOPAD true output hdoutp_ch0; // exemplar attribute hdoutp_ch0 NOPAD true output hdoutn_ch0; // exemplar attribute hdoutn_ch0 NOPAD true output hdoutp_ch1; // exemplar attribute hdoutp_ch1 NOPAD true output hdoutn_ch1; // exemplar attribute hdoutn_ch1 NOPAD true output hdoutp_ch2; // exemplar attribute hdoutp_ch2 NOPAD true output hdoutn_ch2; // exemplar attribute hdoutn_ch2 NOPAD true output hdoutp_ch3; // exemplar attribute hdoutp_ch3 NOPAD true output hdoutn_ch3; // exemplar attribute hdoutn_ch3 NOPAD true // Add your FPGA design module here //synopsys translate_off defparam Xaui_0_inst.USER_CONFIG_FILE = "Xaui_0.txt"; //synopsys translate_on // Add the rest of the PCS pins // Instantiation Xaui_0 Xaui_0_inst ( .refclkp(refclkp), .refclkn(refclkn), .hdinp_ch0(hdinp_ch0), .hdinn_ch0(hdinn_ch0), .hdoutp_ch0(hdoutp_ch0), .hdoutn_ch0(hdoutn_ch0), .sci_sel_ch0(sci_sel_ch0), .rxiclk_ch0(rxiclk_ch0), .txiclk_ch0(txiclk_ch0), .rx_full_clk_ch0(rx_full_clk_ch0), .rx_half_clk_ch0(rx_half_clk_ch0), .tx_full_clk_ch0(tx_full_clk_ch0), .tx_half_clk_ch0(tx_half_clk_ch0), .txdata_ch0(txdata_ch0), .txc_ch0(txc_ch0), .rxdata_ch0(rxdata_ch0), .rxc_ch0(rxc_ch0), .rx_disp_err_ch0(rx_disp_err_ch0), .rx_cv_err_ch0(rx_cv_err_ch0), .rx_serdes_rst_ch0_c(rx_serdes_rst_ch0_c), .tx_pcs_rst_ch0_c(tx_pcs_rst_ch0_c), .tx_pwrup_ch0_c(tx_pwrup_ch0_c), .rx_pcs_rst_ch0_c(rx_pcs_rst_ch0_c), .rx_pwrup_ch0_c(rx_pwrup_ch0_c), .rx_los_low_ch0_s(rx_los_low_ch0_s), .lsm_status_ch0_s(lsm_status_ch0_s), .rx_cdr_lol_ch0_s(rx_cdr_lol_ch0_s), .hdinp_ch1(hdinp_ch1), .hdinn_ch1(hdinn_ch1), .hdoutp_ch1(hdoutp_ch1), .hdoutn_ch1(hdoutn_ch1), .sci_sel_ch1(sci_sel_ch1), .rxiclk_ch1(rxiclk_ch1), .txiclk_ch1(txiclk_ch1), .rx_full_clk_ch1(rx_full_clk_ch1), .rx_half_clk_ch1(rx_half_clk_ch1), .tx_full_clk_ch1(tx_full_clk_ch1), .tx_half_clk_ch1(tx_half_clk_ch1), .txdata_ch1(txdata_ch1), .txc_ch1(txc_ch1), .rxdata_ch1(rxdata_ch1), .rxc_ch1(rxc_ch1), .rx_disp_err_ch1(rx_disp_err_ch1), .rx_cv_err_ch1(rx_cv_err_ch1), .rx_serdes_rst_ch1_c(rx_serdes_rst_ch1_c), .tx_pcs_rst_ch1_c(tx_pcs_rst_ch1_c), .tx_pwrup_ch1_c(tx_pwrup_ch1_c), .rx_pcs_rst_ch1_c(rx_pcs_rst_ch1_c), .rx_pwrup_ch1_c(rx_pwrup_ch1_c), .rx_los_low_ch1_s(rx_los_low_ch1_s), .lsm_status_ch1_s(lsm_status_ch1_s), .rx_cdr_lol_ch1_s(rx_cdr_lol_ch1_s), .hdinp_ch2(hdinp_ch2), .hdinn_ch2(hdinn_ch2), .hdoutp_ch2(hdoutp_ch2), .hdoutn_ch2(hdoutn_ch2), .sci_sel_ch2(sci_sel_ch2), .rxiclk_ch2(rxiclk_ch2), .txiclk_ch2(txiclk_ch2), .rx_full_clk_ch2(rx_full_clk_ch2), .rx_half_clk_ch2(rx_half_clk_ch2), .tx_full_clk_ch2(tx_full_clk_ch2), .tx_half_clk_ch2(tx_half_clk_ch2), .txdata_ch2(txdata_ch2), .txc_ch2(txc_ch2), .rxdata_ch2(rxdata_ch2), .rxc_ch2(rxc_ch2), .rx_disp_err_ch2(rx_disp_err_ch2), .rx_cv_err_ch2(rx_cv_err_ch2), .rx_serdes_rst_ch2_c(rx_serdes_rst_ch2_c), .tx_pcs_rst_ch2_c(tx_pcs_rst_ch2_c), .tx_pwrup_ch2_c(tx_pwrup_ch2_c), .rx_pcs_rst_ch2_c(rx_pcs_rst_ch2_c), .rx_pwrup_ch2_c(rx_pwrup_ch2_c), .rx_los_low_ch2_s(rx_los_low_ch2_s), .lsm_status_ch2_s(lsm_status_ch2_s), .rx_cdr_lol_ch2_s(rx_cdr_lol_ch2_s), .hdinp_ch3(hdinp_ch3), .hdinn_ch3(hdinn_ch3), .hdoutp_ch3(hdoutp_ch3), .hdoutn_ch3(hdoutn_ch3), .sci_sel_ch3(sci_sel_ch3), .rxiclk_ch3(rxiclk_ch3), .txiclk_ch3(txiclk_ch3), .rx_full_clk_ch3(rx_full_clk_ch3), .rx_half_clk_ch3(rx_half_clk_ch3), .tx_full_clk_ch3(tx_full_clk_ch3), .tx_half_clk_ch3(tx_half_clk_ch3), .txdata_ch3(txdata_ch3), .txc_ch3(txc_ch3), .rxdata_ch3(rxdata_ch3), .rxc_ch3(rxc_ch3), .rx_disp_err_ch3(rx_disp_err_ch3), .rx_cv_err_ch3(rx_cv_err_ch3), .rx_serdes_rst_ch3_c(rx_serdes_rst_ch3_c), .tx_pcs_rst_ch3_c(tx_pcs_rst_ch3_c), .tx_pwrup_ch3_c(tx_pwrup_ch3_c), .rx_pcs_rst_ch3_c(rx_pcs_rst_ch3_c), .rx_pwrup_ch3_c(rx_pwrup_ch3_c), .rx_los_low_ch3_s(rx_los_low_ch3_s), .lsm_status_ch3_s(lsm_status_ch3_s), .rx_cdr_lol_ch3_s(rx_cdr_lol_ch3_s), .sci_wrdata(sci_wrdata), .sci_addr(sci_addr), .sci_rddata(sci_rddata), .sci_sel_quad(sci_sel_quad), .sci_rd(sci_rd), .sci_wrn(sci_wrn), .sci_int(sci_int), .tx_serdes_rst_c(tx_serdes_rst_c), .tx_pll_lol_qd_s(tx_pll_lol_qd_s), .tx_sync_qd_c(tx_sync_qd_c), .refclk2fpga(refclk2fpga), .serdes_rst_qd_c(serdes_rst_qd_c), .rst_qd_c(rst_qd_c) ); endmodule

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