Verilog_code
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：42KB
下载次数：8
上传日期：2011-04-22 10:48:16
上 传 者：
zhuanchunqiu
说明： 著名教材数字逻辑基础与Verilog设计(原书第2版) 附录源码
(The basis of well-known materials and Verilog digital logic design (the original version 2) Appendix source)
文件列表:
Verilog_code\AppendixA\figA_11.v (448, 2007-03-14)
Verilog_code\AppendixA\figA_12.v (277, 2007-03-14)
Verilog_code\AppendixA\figA_13.v (457, 2007-03-14)
Verilog_code\AppendixA\figA_14.v (273, 2007-03-14)
Verilog_code\AppendixA\figA_18.v (555, 2007-03-14)
Verilog_code\AppendixA\figA_19.v (698, 2007-03-14)
Verilog_code\AppendixA\figA_2.v (169, 2007-03-14)
Verilog_code\AppendixA\figA_20.v (466, 2007-03-14)
Verilog_code\AppendixA\figA_21.v (504, 2007-03-14)
Verilog_code\AppendixA\figA_22.v (370, 2007-03-14)
Verilog_code\AppendixA\figA_23.v (535, 2007-03-14)
Verilog_code\AppendixA\figA_24.v (573, 2007-03-14)
Verilog_code\AppendixA\figA_25.v (730, 2007-03-14)
Verilog_code\AppendixA\figA_26.v (602, 2007-03-14)
Verilog_code\AppendixA\figA_27.v (127, 2007-03-14)
Verilog_code\AppendixA\figA_28.v (125, 2007-03-14)
Verilog_code\AppendixA\figA_29.v (209, 2007-03-14)
Verilog_code\AppendixA\figA_3.v (126, 2007-03-14)
Verilog_code\AppendixA\figA_30.v (193, 2007-03-14)
Verilog_code\AppendixA\figA_31.v (201, 2007-03-14)
Verilog_code\AppendixA\figA_32.v (221, 2007-03-14)
Verilog_code\AppendixA\figA_33.v (261, 2007-03-14)
Verilog_code\AppendixA\figA_34.v (186, 2007-03-14)
Verilog_code\AppendixA\figA_35.v (183, 2007-03-14)
Verilog_code\AppendixA\figA_36.v (220, 2007-03-14)
Verilog_code\AppendixA\figA_38.v (1309, 2007-03-14)
Verilog_code\AppendixA\figA_4.v (272, 2007-03-14)
Verilog_code\AppendixA\figA_40.v (556, 2007-03-14)
Verilog_code\AppendixA\figA_41.v (528, 2007-03-14)
Verilog_code\AppendixA\figA_43.v (626, 2007-03-14)
Verilog_code\AppendixA\figA_5.v (219, 2007-03-14)
Verilog_code\AppendixA\figA_6.v (169, 2007-03-14)
Verilog_code\AppendixA\figA_7.v (195, 2007-03-14)
Verilog_code\AppendixA\figA_9.v (171, 2007-03-14)
Verilog_code\Chapter10\fig10_13.v (1494, 2007-03-14)
Verilog_code\Chapter10\fig10_19.v (2380, 2007-03-14)
Verilog_code\Chapter10\fig10_2.v (201, 2007-03-14)
Verilog_code\Chapter10\fig10_28.v (2850, 2007-03-14)
Verilog_code\Chapter10\fig10_3.v (245, 2007-03-14)
Verilog_code\Chapter10\fig10_40.v (3657, 2007-03-14)
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