encoder_clk
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：528KB
下载次数：2
上传日期：2017-08-02 10:10:10
上 传 者：
没伞的孩子
说明： 精确实现奇数分频，将FPGA开发板提供的25MHZ时钟分频为1MHZ，内含测试文件
(Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files)
文件列表:
encoder_clk (0, 2017-08-02)
encoder_clk\encoder_clk (0, 2017-08-02)
encoder_clk\encoder_clk\code (0, 2017-08-02)
encoder_clk\encoder_clk\code\test.v (1061, 2017-06-28)
encoder_clk\encoder_clk\code\test_clk.v (914, 2017-06-26)
encoder_clk\encoder_clk\code\yinjian.ucf (153, 2017-06-26)
encoder_clk\encoder_clk\encoder_clk.gise (15929, 2017-07-20)
encoder_clk\encoder_clk\encoder_clk.xise (34627, 2017-06-28)
encoder_clk\encoder_clk\fuse.log (1185, 2017-06-28)
encoder_clk\encoder_clk\fuse.xmsgs (367, 2017-06-28)
encoder_clk\encoder_clk\fuseRelaunch.cmd (254, 2017-06-28)
encoder_clk\encoder_clk\ipcore_dir (0, 2017-06-26)
encoder_clk\encoder_clk\iseconfig (0, 2017-08-02)
encoder_clk\encoder_clk\iseconfig\encoder_clk.projectmgr (7766, 2017-07-20)
encoder_clk\encoder_clk\iseconfig\test_clk.xreport (20596, 2017-07-20)
encoder_clk\encoder_clk\isim (0, 2017-08-02)
encoder_clk\encoder_clk\isim.cmd (44, 2017-07-20)
encoder_clk\encoder_clk\isim.log (432, 2017-07-20)
encoder_clk\encoder_clk\isim\isim_usage_statistics.html (1666, 2017-07-20)
encoder_clk\encoder_clk\isim\pn_info (6, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim (0, 2017-08-02)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\isimcrash.log (0, 2017-07-20)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\ISimEngine-DesignHierarchy.dbg (4230, 2017-07-20)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\isimkernel.log (561, 2017-07-20)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\libPortability.dll (901120, 2012-10-13)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\netId.dat (28, 2017-07-20)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\test_isim_beh.exe (118169, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\tmp_save (0, 2017-08-02)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\tmp_save\_1 (2157, 2017-07-20)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work (0, 2017-08-02)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000000867157637_1985558087.c (4583, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000000867157637_1985558087.didat (2924, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000000867157637_1985558087.nt64.obj (2060, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000002145102365_1765943307.c (7239, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000002145102365_1765943307.didat (2800, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000002145102365_1765943307.nt64.obj (2473, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000004134447467_2073120511.c (7958, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000004134447467_2073120511.didat (5496, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\m_00000000004134447467_2073120511.nt64.obj (2794, 2017-06-28)
encoder_clk\encoder_clk\isim\test_isim_beh.exe.sim\work\test_isim_beh.exe_main.c (1353, 2017-06-28)
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