sp6ex15
所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:4579KB
下载次数:5
上传日期:2017-08-02 10:29:57
上 传 者:
没伞的孩子
说明: SRAM读写测试,每秒进行一次单字节SRAM读写,使用chipscope观察时序波形
(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)
文件列表:
sp6ex15\counter.lso (6, 2015-05-19)
sp6ex15\counter.prj (38, 2015-05-19)
sp6ex15\counter.stx (1693, 2015-05-19)
sp6ex15\counter.xst (1144, 2015-05-19)
sp6ex15\ipcore_dir\chipscope_debug.cdc (5118, 2015-06-06)
sp6ex15\ipcore_dir\coregen.cgp (237, 2015-05-11)
sp6ex15\ipcore_dir\coregen.log (191, 2015-05-27)
sp6ex15\ipcore_dir\create_pll_controller.tcl (1262, 2015-05-11)
sp6ex15\ipcore_dir\edit_pll_controller.tcl (1129, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\doc\clk_wiz_v3_6_vinfo.html (6789, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\doc\pg065_clk_wiz.pdf (42657, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\example_design\pll_controller_exdes.ucf (2648, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\example_design\pll_controller_exdes.v (6406, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\example_design\pll_controller_exdes.xdc (3164, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\implement.bat (3664, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\implement.sh (3543, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\planAhead_ise.bat (2695, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\planAhead_ise.sh (2603, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\planAhead_ise.tcl (3119, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\planAhead_rdn.bat (2690, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\planAhead_rdn.sh (2595, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\planAhead_rdn.tcl (3257, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\xst.prj (92, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\implement\xst.scr (183, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simcmds.tcl (150, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_isim.bat (2798, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_isim.sh (2681, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_mti.bat (2783, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_mti.do (2707, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_mti.sh (2653, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_ncsim.sh (2785, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\simulate_vcs.sh (2924, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\ucli_commands.key (105, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\vcs_session.tcl (1132, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\wave.do (2920, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\functional\wave.sv (4624, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\pll_controller_tb.v (5017, 2015-05-27)
sp6ex15\ipcore_dir\pll_controller\simulation\timing\pll_controller_tb.v (5506, 2015-05-27)
... ...
The following files were generated for 'icon_pro' in directory
E:\ds\xilinx_sp6\prj\sp6_sram_sigle\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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