BMD_design_gen2_x4_with_Chipscope
所属分类:VHDL/FPGA/Verilog
开发工具:WINDOWS
文件大小:9157KB
下载次数:13
上传日期:2017-08-03 09:53:25
上 传 者:
q250891510
说明: PCIE BDM官方实例,xapp1052
(PCIE BDM XAPP1052 FROM XILINX)
文件列表:
BMD_design_gen2_x4_Chipscope\bmd.cdc (30571, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD.v (12337, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_64_RX_ENGINE.v (17139, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_64_TX_ENGINE.v (27266, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_CFG_CTRL.v (5098, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_design_gen2_x4.gise (15286, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_design_gen2_x4.xise (41924, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_EP.v (25469, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_EP_MEM.v (25212, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_EP_MEM_ACCESS.v (16932, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_GEN2.v (9087, 2014-08-06)
BMD_design_gen2_x4_Chipscope\BMD_INTR_CTRL.v (8647, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_INTR_CTRL_DELAY.v (3398, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_PCIE_20.v (1083, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_RD_THROTTLE.v (7624, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_TO_CTRL.v (2379, 2009-10-22)
BMD_design_gen2_x4_Chipscope\BMD_TX_ENGINE_summary.html (4105, 2014-08-06)
BMD_design_gen2_x4_Chipscope\gtx_drp_chanalign_fix_3752_v6.v (6942, 2014-08-05)
BMD_design_gen2_x4_Chipscope\gtx_rx_valid_filter_v6.v (12103, 2014-08-05)
BMD_design_gen2_x4_Chipscope\gtx_tx_sync_rate_v6.v (14596, 2014-08-05)
BMD_design_gen2_x4_Chipscope\gtx_wrapper_v6.v (26511, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_2_0_v6.v (82207, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.cmd_log (193, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.lso (6, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.ngc (944004, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.ngr (1239650, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.prj (373, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.stx (0, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.syr (82960, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6.xst (1085, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6_envsettings.html (9075, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6_summary.html (5711, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_app_v6_xst.xrpt (16513, 2014-08-06)
BMD_design_gen2_x4_Chipscope\pcie_brams_v6.v (8684, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_bram_top_v6.v (6038, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_bram_v6.v (11739, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_clocking_v6.v (11538, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_gtx_v6.v (24312, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_pipe_lane_v6.v (12792, 2014-08-05)
BMD_design_gen2_x4_Chipscope\pcie_pipe_misc_v6.v (7726, 2014-08-05)
... ...
The following files were generated for 'icon_pro' in directory
E:\xapp1052\BMD_design_gen2_x4_Chipscope\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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