E_2011
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：689KB
下载次数：3
上传日期：2017-08-04 16:25:10
上 传 者：
安珍妮
说明： 生成了一个M序列，适用于2011年全国电子设计竞赛的F题
(A M sequence is generated that applies to the F question of the 2011 National Electronic Design Competition)
文件列表:
E_2011 (0, 2017-08-01)
E_2011\CLK_M.v (887, 2017-07-26)
E_2011\E_2011.bld (1017, 2017-07-26)
E_2011\E_2011.cmd_log (46494, 2017-07-26)
E_2011\E_2011.gise (11838, 2017-08-01)
E_2011\E_2011.lso (6, 2017-07-26)
E_2011\E_2011.ncd (24874, 2017-07-26)
E_2011\E_2011.ngc (28308, 2017-07-26)
E_2011\E_2011.ngd (42166, 2017-07-26)
E_2011\E_2011.ngr (23850, 2017-07-26)
E_2011\E_2011.pad (11507, 2017-07-26)
E_2011\E_2011.par (8901, 2017-07-26)
E_2011\E_2011.pcf (1512, 2017-07-26)
E_2011\E_2011.prj (73, 2017-07-26)
E_2011\E_2011.ptwx (16866, 2017-07-26)
E_2011\E_2011.stx (0, 2017-07-26)
E_2011\E_2011.syr (19712, 2017-07-26)
E_2011\E_2011.twr (41154, 2017-07-26)
E_2011\E_2011.twx (61718, 2017-07-26)
E_2011\E_2011.unroutes (361, 2017-07-26)
E_2011\E_2011.ut (553, 2017-07-26)
E_2011\E_2011.v (872, 2017-07-26)
E_2011\E_2011.xise (36303, 2017-07-31)
E_2011\E_2011.xpi (46, 2017-07-26)
E_2011\E_2011.xst (1067, 2017-07-26)
E_2011\E_2011_bitgen.xwbt (281, 2017-07-26)
E_2011\E_2011_envsettings.html (16938, 2017-08-01)
E_2011\E_2011_guide.ncd (24874, 2017-07-26)
E_2011\E_2011_map.map (6916, 2017-07-26)
E_2011\E_2011_map.mrp (10035, 2017-07-26)
E_2011\E_2011_map.ncd (16534, 2017-07-26)
E_2011\E_2011_map.ngm (74771, 2017-07-26)
E_2011\E_2011_map.xrpt (21699, 2017-07-26)
E_2011\E_2011_ngdbuild.xrpt (7774, 2017-07-26)
E_2011\E_2011_pad.csv (11539, 2017-07-26)
E_2011\E_2011_pad.txt (51777, 2017-07-26)
E_2011\E_2011_par.xrpt (128112, 2017-07-26)
E_2011\E_2011_summary.html (17837, 2017-08-01)
E_2011\E_2011_summary.xml (410, 2017-07-26)
E_2011\E_2011_usage.xml (46611, 2017-07-26)
... ...
The following files were generated for 'ila' in directory
F:\AX309.161219\AX309\09_VERILOG\module\E_2011\ipcore_dir\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* ila.cdc
* ila.constraints/ila.ucf
* ila.constraints/ila.xdc
* ila.ncf
* ila.ngc
* ila.ucf
* ila.v
* ila.veo
* ila.xdc
* ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* ila.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* ila.sym
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* ila.gise
* ila.xise
Deliver Readme:
Readme file for the IP.
* ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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