27_adda_test
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：5833KB
下载次数：5
上传日期：2017-08-04 16:26:41
上 传 者：
安珍妮
说明： ADDA模块的代码，适用于黑金FPGA开发板，35M采样速率
(The ADDA module code applies to the black gold FPGA development board, the 35M sampling rate)
文件列表:
27_adda_test (0, 2017-07-23)
27_adda_test\_ngo (0, 2017-07-21)
27_adda_test\_ngo\netlist.lst (312, 2017-07-21)
27_adda_test\_xmsgs (0, 2017-07-21)
27_adda_test\_xmsgs\bitgen.xmsgs (1258, 2017-07-21)
27_adda_test\_xmsgs\map.xmsgs (7067, 2017-07-21)
27_adda_test\_xmsgs\ngdbuild.xmsgs (1830, 2017-07-21)
27_adda_test\_xmsgs\par.xmsgs (367, 2017-07-21)
27_adda_test\_xmsgs\pn_parser.xmsgs (1203, 2017-07-23)
27_adda_test\_xmsgs\trce.xmsgs (1030, 2017-07-21)
27_adda_test\_xmsgs\xst.xmsgs (4476, 2017-07-21)
27_adda_test\adda.cpj (143707, 2015-11-04)
27_adda_test\adda_test.bgn (7563, 2017-07-21)
27_adda_test\adda_test.bit (340995, 2017-07-21)
27_adda_test\adda_test.bld (2137, 2017-07-21)
27_adda_test\adda_test.cmd_log (17205, 2017-07-21)
27_adda_test\adda_test.drc (776, 2017-07-21)
27_adda_test\adda_test.gise (13241, 2017-07-23)
27_adda_test\adda_test.lso (6, 2017-07-21)
27_adda_test\adda_test.ncd (601193, 2017-07-21)
27_adda_test\adda_test.ngc (36414, 2017-07-21)
27_adda_test\adda_test.ngd (1867202, 2017-07-21)
27_adda_test\adda_test.ngr (28331, 2017-07-21)
27_adda_test\adda_test.pad (11926, 2017-07-21)
27_adda_test\adda_test.par (11483, 2017-07-21)
27_adda_test\adda_test.pcf (223794, 2017-07-21)
27_adda_test\adda_test.prj (192, 2017-07-21)
27_adda_test\adda_test.ptwx (18391, 2017-07-21)
27_adda_test\adda_test.stx (0, 2017-07-21)
27_adda_test\adda_test.syr (34734, 2017-07-21)
27_adda_test\adda_test.twr (36575, 2017-07-21)
27_adda_test\adda_test.twx (50928, 2017-07-21)
27_adda_test\adda_test.ucf (1764, 2015-11-04)
27_adda_test\adda_test.unroutes (161, 2017-07-21)
27_adda_test\adda_test.ut (553, 2017-07-21)
27_adda_test\adda_test.v (1893, 2017-07-21)
27_adda_test\adda_test.xise (37488, 2017-07-21)
27_adda_test\adda_test.xpi (46, 2017-07-21)
27_adda_test\adda_test.xst (1098, 2017-07-21)
27_adda_test\adda_test_bitgen.xwbt (305, 2017-07-21)
... ...
The following files were generated for 'FIR' in directory
F:\AX309.161219\AX309\09_VERILOG\module\27_adda_test\ipcore_dir\
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* FIR.mif
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* FIR.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* FIR.ngc
* FIR.v
* FIR.veo
* FIRCOEFF_auto0_0.mif
* FIRCOEFF_auto0_1.mif
* FIRCOEFF_auto0_2.mif
* FIRCOEFF_auto0_3.mif
* FIRfilt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* FIR.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* FIR.asy
* FIR.mif
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* FIR.sym
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* FIR_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* FIR.gise
* FIR.xise
* _xmsgs/pn_parser.xmsgs
Deliver Readme:
Readme file for the IP.
* FIR_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* FIR_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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