文件列表:

fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_10KHz_4VPP_a_2V10.prn (443100, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_10KHz_4VPP_b_2V10.prn (443035, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_1KHz_4VPP_a_2V10.prn (443214, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_1KHz_4VPP_b_2V10.prn (443136, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_200Hz_4VPP_a_2V10.prn (444581, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_200Hz_4VPP_b_2V10.prn (444563, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_20KHz_4VPP_a_2V10.prn (443058, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_20KHz_4VPP_b_2V10.prn (443012, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_2KHz_4VPP_a_2V10.prn (443083, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_2KHz_4VPP_b_2V10.prn (443089, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_500Hz_4VPP_a_2V10.prn (443298, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_500Hz_4VPP_b_2V10.prn (443307, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_50Hz_4VPP_a_2V10.prn (455503, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_50Hz_4VPP_b_2V10.prn (454537, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_5KHz_4VPP_a_2V10.prn (443133, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\adc_test\1Msps_5KHz_4VPP_b_2V10.prn (443076, 2015-12-30)
fin\ADC_1M_FMC_V1.0_1Msps\impact.xsl (1477, 2017-03-18)
fin\ADC_1M_FMC_V1.0_1Msps\impact_impact.xwbt (236, 2017-03-18)
fin\ADC_1M_FMC_V1.0_1Msps\output.txt (122, 2016-04-01)
fin\ADC_1M_FMC_V1.0_1Msps\par\.lso (6, 2017-03-06)
fin\ADC_1M_FMC_V1.0_1Msps\par\0 (0, 2017-03-06)
fin\ADC_1M_FMC_V1.0_1Msps\par\21 (0, 2017-03-08)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9148.coe (857, 2015-05-26)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9148_rom.mif (2196, 2015-05-26)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9520.coe (534, 2015-05-26)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9520_rom.mif (1690, 2015-05-26)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9650_adc.coe (244, 2014-09-25)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9650_adc1.coe (244, 2015-12-25)
fin\ADC_1M_FMC_V1.0_1Msps\par\ad9650_rom.mif (390, 2015-12-24)
fin\ADC_1M_FMC_V1.0_1Msps\par\adctest.cpj (15645, 2016-08-18)
fin\ADC_1M_FMC_V1.0_1Msps\par\ccdc.cdc (551, 2016-04-01)
fin\ADC_1M_FMC_V1.0_1Msps\par\cdc.cdc (6145, 2016-04-01)
fin\ADC_1M_FMC_V1.0_1Msps\par\DFE_top.cmd_log (828, 2016-01-27)
fin\ADC_1M_FMC_V1.0_1Msps\par\DFE_top.prj (76, 2017-03-06)
fin\ADC_1M_FMC_V1.0_1Msps\par\DFE_top.stx (1272, 2017-03-06)
fin\ADC_1M_FMC_V1.0_1Msps\par\DFE_top.tfi (313, 2016-01-27)
fin\ADC_1M_FMC_V1.0_1Msps\par\DFE_top.xst (153, 2017-03-06)
fin\ADC_1M_FMC_V1.0_1Msps\par\edkBmmFile.bmm (1418, 2015-06-05)
fin\ADC_1M_FMC_V1.0_1Msps\par\edkBmmFile_bd.bmm (2273, 2015-06-05)
fin\ADC_1M_FMC_V1.0_1Msps\par\edk_module\.metadata\.lock (0, 2015-06-05)
... ...

The following files were generated for 'dds' in directory E:\FPGA_train\ADC_1M_FMC_V1.0_1Msps\par\ipcore_dir\ Generate XCO file: CORE Generator input file containing the parameters used to generate a core. * dds.xco Generate Implementation Netlist: Binary Xilinx implementation netlist files containing the information required to implement the module in a Xilinx (R) FPGA. * dds.ngc Obfuscate Netlist Generator: Please see the core data sheet. * dds.ngc Generate Instantiation Templates: Template files containing code that can be used as a model for instantiating a CORE Generator module in an HDL design. * dds.veo RTL Simulation Model Generator: Please see the core data sheet. * dds.v All Documents Generator: Please see the core data sheet. * dds/doc/dds_compiler_v4_0_vinfo.html * dds/doc/dds_ds558.pdf Deliver IP Symbol: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. * dds.asy SYM file generator: Generate a SYM file for compatibility with legacy flows * dds.sym Generate XMDF file: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. * dds_xmdf.tcl Generate ISE project file: ISE Project Navigator support files. These are generated files and should not be edited directly. * _xmsgs/pn_parser.xmsgs * dds.gise * dds.xise Deliver Readme: Readme file for the IP. * dds_readme.txt Generate FLIST file: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. * dds_flist.txt Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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