文件列表:

DE5Net_Conv_Accelerator (0, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit (0, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit\filters.xml (66, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit\mem_system.xml (82954, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit\mem_system_schematic.nlv (30976, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit\pcie_system.xml (83393, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit\pcie_system_schematic.nlv (0, 2017-01-28)
DE5Net_Conv_Accelerator\.qsys_edit\preferences.xml (534, 2017-01-28)
DE5Net_Conv_Accelerator\Clock_hw.tcl (2326, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.SDC (6670, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.dpf (1319, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.htm (36760, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qpf (121, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qsf (43568, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.sld (586, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.v (75536, 2017-01-28)
DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator_assignment_defaults.qdf (54291, 2017-01-28)
DE5Net_Conv_Accelerator\avalon_bridge.v (3012, 2017-01-28)
DE5Net_Conv_Accelerator\avalon_bridge_hw.tcl (8901, 2017-01-28)
DE5Net_Conv_Accelerator\bit_width.vh (341, 2017-01-28)
DE5Net_Conv_Accelerator\cent_ctrl.v (20130, 2017-01-28)
DE5Net_Conv_Accelerator\cent_ctrl_hw.tcl (14937, 2017-01-28)
DE5Net_Conv_Accelerator\clock.v (82, 2017-01-28)
DE5Net_Conv_Accelerator\cnn_parameters.vh (837, 2017-01-28)
DE5Net_Conv_Accelerator\conv.v (15934, 2017-01-28)
DE5Net_Conv_Accelerator\conv_old.v (14910, 2017-01-28)
DE5Net_Conv_Accelerator\db (0, 2017-01-28)
DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.db_info (141, 2017-01-28)
DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.sld_design_entry.sci (227, 2017-01-28)
DE5Net_Conv_Accelerator\fifo_v2.qip (428, 2017-01-28)
DE5Net_Conv_Accelerator\fifo_v2.v (6514, 2017-01-28)
DE5Net_Conv_Accelerator\ifm_loader.v (778, 2017-01-28)
DE5Net_Conv_Accelerator\main_state_actions.v (4501, 2017-01-28)
DE5Net_Conv_Accelerator\main_state_machine.v (3341, 2017-01-28)
DE5Net_Conv_Accelerator\main_states.vh (503, 2017-01-28)
DE5Net_Conv_Accelerator\mem_init.mif (4488830, 2017-01-28)
DE5Net_Conv_Accelerator\mem_system.qsys (325795, 2017-01-28)
DE5Net_Conv_Accelerator\mem_system.sopcinfo (2830888, 2017-01-28)
... ...

# README # * Open DE5Net_Conv_Accelerator/DE5Net_Conv_Accelerator.qsf with *Quartus v16.0.0* on **Computer 1** * Generate Qsys System *mem_system* * Perform Full Compilation * Use computer 1 to program the FPGA device installed on HOST Computer (**Computer 2**) via the USB-Blaster cable. NOTE: This will cause the host computer Kernel to reset and it will automatically reboot. Please save all you work before proceeding with this * Reboot the host computer to train the PCIe link with FPGA board. * Install PCI-Express linux driver on Host PC (**Computer 2**) * Program the FPGA and reboot as mentioned above before performing the installation * Install instructions present in README * Refer to *Using the User Application* pdf for instructions on data transfer. This project is a FPGA based implementation of first Convolutional Layer of AlexNet. The accelerator is developed using Verilog. ## Contact Currently Mr. Sachin Kumawat is developing this project. If you have question or need further information, please contact him. Email: skumawat@ucdavis.edu ## Citing Our [research group](http://lepsucd.com) is working on acceleration of deep CNNs. If this project helped your research, please kindly cite our latest conference paper: ``` Mohammad Motamedi, Philipp Gysel, Venkatesh Akella and Soheil Ghiasi, “Design Space Exploration of FPGA-Based Deep Convolutional Neural Network”, IEEE/ACM Asia-South Pacific Design Automation Conference (ASPDAC), January 2016. ```

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