DDS
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：38377KB
下载次数：13
上传日期：2017-09-07 21:31:35
上 传 者：
灵风轩允
说明： 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来
(Verilog realizes DDS Signal Generator)
文件列表:
DDS (0, 2017-09-07)
DDS\control.cmd_log (585, 2015-03-31)
DDS\control.tfi (666, 2015-03-31)
DDS\control.v (9329, 2015-04-01)
DDS\Con_Amp.cmd_log (195, 2015-03-25)
DDS\Con_Amp.tfi (163, 2015-03-25)
DDS\Con_Amp.v (832, 2015-03-28)
DDS\Con_Freq.cmd_log (198, 2015-03-25)
DDS\Con_Freq.tfi (137, 2015-03-25)
DDS\Con_Freq.v (791, 2015-03-25)
DDS\dds.cmd_log (183, 2015-03-21)
DDS\DDS.gise (16646, 2015-08-12)
DDS\dds.lso (6, 2015-03-21)
DDS\dds.prj (22, 2015-03-21)
DDS\dds.stx (1648, 2015-03-21)
DDS\dds.tfi (125, 2015-03-21)
DDS\DDS.v (751, 2015-03-21)
DDS\DDS.xise (41978, 2015-04-02)
DDS\dds.xst (1121, 2015-03-21)
DDS\DDS_summary.html (3517, 2015-03-21)
DDS\dds_top.bgn (7562, 2015-04-02)
DDS\dds_top.bit (464862, 2015-04-02)
DDS\DDS_top.bld (1025, 2015-04-02)
DDS\DDS_top.cmd_log (44294, 2015-04-02)
DDS\DDS_top.cpj (63173, 2015-03-30)
DDS\dds_top.drc (775, 2015-04-02)
DDS\DDS_top.lso (6, 2015-04-02)
DDS\DDS_top.ncd (2213728, 2015-04-02)
DDS\DDS_top.ngc (2199903, 2015-04-02)
DDS\DDS_top.ngd (4076163, 2015-04-02)
DDS\DDS_top.ngr (3562751, 2015-04-02)
DDS\DDS_top.pad (14742, 2015-04-02)
DDS\DDS_top.par (11566, 2015-04-02)
DDS\DDS_top.pcf (151679, 2015-04-02)
DDS\DDS_top.prj (554, 2015-04-02)
DDS\DDS_top.ptwx (19002, 2015-04-02)
DDS\DDS_top.stx (0, 2015-04-02)
DDS\DDS_top.syr (135079, 2015-04-02)
DDS\DDS_top.tfi (142, 2015-03-25)
DDS\DDS_top.twr (152764, 2015-04-02)
... ...
The following files were generated for 'chufa' in directory
E:\VerilogProgram\DDS\ipcore_dir\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chufa.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chufa.ngc
* chufa.v
* chufa.veo
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* chufa.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chufa.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* chufa.sym
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* chufa_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* chufa.gise
* chufa.xise
Deliver Readme:
Readme file for the IP.
* chufa_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chufa_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：