FPGA_SWD
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：151KB
下载次数：0
上传日期：2017-09-16 00:00:08
上 传 者：
sh-1993
说明： 用于更快SWD编程的fpga协处理器
(fpga co-processor for faster SWD programming)
文件列表:
Top.v (65492, 2017-09-16)
build.sbt (812, 2017-09-16)
fpga_swd_2 (0, 2017-09-16)
fpga_swd_2\fpga_swd.h (1789, 2017-09-16)
fpga_swd_2\fpga_swd_2.ino (2800, 2017-09-16)
icestick.pcf (1867, 2017-09-16)
project (0, 2017-09-16)
project\build.properties (22, 2017-09-16)
project\plugins.sbt (22, 2017-09-16)
project\project (0, 2017-09-16)
project\project\target (0, 2017-09-16)
project\project\target\config-classes (0, 2017-09-16)
project\project\target\config-classes\$11933bf543191ceb629c$$anonfun$$sbtdef$1.class (1034, 2017-09-16)
project\project\target\config-classes\$11933bf543191ceb629c$.class (1316, 2017-09-16)
project\project\target\config-classes\$11933bf543191ceb629c.cache (22, 2017-09-16)
project\project\target\config-classes\$11933bf543191ceb629c.class (724, 2017-09-16)
project\target (0, 2017-09-16)
project\target\config-classes (0, 2017-09-16)
project\target\config-classes\$052a44782576165ef6f2$$anonfun$$sbtdef$1.class (1516, 2017-09-16)
project\target\config-classes\$052a44782576165ef6f2$.class (1528, 2017-09-16)
project\target\config-classes\$052a44782576165ef6f2.cache (22, 2017-09-16)
project\target\config-classes\$052a44782576165ef6f2.class (392, 2017-09-16)
project\target\config-classes\$1a69ab55e3e6247115a5$$anonfun$$sbtdef$1.class (879, 2017-09-16)
project\target\config-classes\$1a69ab55e3e6247115a5$.class (1305, 2017-09-16)
project\target\config-classes\$1a69ab55e3e6247115a5.cache (22, 2017-09-16)
project\target\config-classes\$1a69ab55e3e6247115a5.class (392, 2017-09-16)
project\target\config-classes\$4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1$$anonfun$apply$1.class (1562, 2017-09-16)
project\target\config-classes\$4fbf35c5103c86f5cb40$$anonfun$$sbtdef$1.class (1095, 2017-09-16)
project\target\config-classes\$4fbf35c5103c86f5cb40$.class (1509, 2017-09-16)
project\target\config-classes\$4fbf35c5103c86f5cb40.cache (22, 2017-09-16)
project\target\config-classes\$4fbf35c5103c86f5cb40.class (714, 2017-09-16)
project\target\config-classes\$81eec9ef00c970e0dbd8$$anonfun$$sbtdef$1.class (1759, 2017-09-16)
project\target\config-classes\$81eec9ef00c970e0dbd8$.class (1538, 2017-09-16)
project\target\config-classes\$81eec9ef00c970e0dbd8.cache (22, 2017-09-16)
project\target\config-classes\$81eec9ef00c970e0dbd8.class (392, 2017-09-16)
project\target\config-classes\$ac15debf6f88ea3e5bfd$$anonfun$$sbtdef$1.class (882, 2017-09-16)
project\target\config-classes\$ac15debf6f88ea3e5bfd$.class (1310, 2017-09-16)
project\target\config-classes\$ac15debf6f88ea3e5bfd.cache (22, 2017-09-16)
... ...
# FPGA_SWD
fpga based SWD programmer
This setup works up to above the max of SWD spec (50Mhz)
currently verified working with at ATSAMD21G18 at 170 kB/sec. Programs the whole 256k in ~1.5sec.
That may be the max for that chip or maybe limited a bit by my hardware setup. I'll try again once I get a proper PCB.
近期下载者：
相关文件：
收藏者：