hdl-2015_r2
所属分类：VHDL/FPGA/Verilog
开发工具：Vivado
文件大小：1361KB
下载次数：9
上传日期：2017-09-18 18:02:47
上 传 者：
小陈3
说明： AD9361 IP核，Windows版本，Vivado2015.2
(AD9361 IP core, used on Windows, Vivado2015.2)
文件列表:
hdl-2015_r2 (0, 2016-03-07)
hdl-2015_r2\LICENSE (1914, 2016-03-07)
hdl-2015_r2\Makefile (1327, 2016-03-07)
hdl-2015_r2\library (0, 2016-03-07)
hdl-2015_r2\library\Makefile (3899, 2016-03-07)
hdl-2015_r2\library\axi_ad6676 (0, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\Makefile (1526, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\axi_ad6676.v (9637, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\axi_ad6676_channel.v (5407, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\axi_ad6676_constr.xdc (0, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\axi_ad6676_if.v (4159, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\axi_ad6676_ip.tcl (1045, 2016-03-07)
hdl-2015_r2\library\axi_ad6676\axi_ad6676_pnmon.v (7006, 2016-03-07)
hdl-2015_r2\library\axi_ad9122 (0, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\Makefile (1723, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\axi_ad9122.v (9972, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\axi_ad9122_channel.v (9618, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\axi_ad9122_constr.xdc (174, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\axi_ad9122_core.v (8585, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\axi_ad9122_if.v (7447, 2016-03-07)
hdl-2015_r2\library\axi_ad9122\axi_ad9122_ip.tcl (1412, 2016-03-07)
hdl-2015_r2\library\axi_ad9144 (0, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\Makefile (1585, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144.v (10643, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144_channel.v (21676, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144_constr.xdc (2175, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144_core.v (9513, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144_hw.tcl (5502, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144_if.v (5623, 2016-03-07)
hdl-2015_r2\library\axi_ad9144\axi_ad9144_ip.tcl (1120, 2016-03-07)
hdl-2015_r2\library\axi_ad9152 (0, 2016-03-07)
hdl-2015_r2\library\axi_ad9152\Makefile (1585, 2016-03-07)
hdl-2015_r2\library\axi_ad9152\axi_ad9152.v (7447, 2016-03-07)
hdl-2015_r2\library\axi_ad9152\axi_ad9152_channel.v (21676, 2016-03-07)
hdl-2015_r2\library\axi_ad9152\axi_ad9152_constr.xdc (2174, 2016-03-07)
hdl-2015_r2\library\axi_ad9152\axi_ad9152_core.v (7329, 2016-03-07)
hdl-2015_r2\library\axi_ad9152\axi_ad9152_if.v (4487, 2016-03-07)
... ...
#HDL Reference Designs
Analog Devices HDL libraries and projects
###Tools version:
- **Xilinx** : [Vivado 2015.2.1]
- **Altera** : [Quartus 15.0]
###Documentation and support
For first time users, it is **highly recommended** to go through our [HDL user guide].
For support please visit our [FPGA Reference Designs Support Community] on EngineerZone.
[Vivado 2015.2.1]:http://www.xilinx.com/content/xilinx/en/downloadNav/vivado-design-tools/2015-2.html
[Quartus 15.0]:http://dl.altera.com/15.0/?edition=subscription
[HDL user guide]:http://wiki.analog.com/resources/fpga/docs/hdl
[FPGA Reference Designs Support Community]:http://ez.analog.com/community/fpga
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