hdl-2016_r2
所属分类：VHDL/FPGA/Verilog
开发工具：Vivado
文件大小：1703KB
下载次数：21
上传日期：2017-09-18 18:04:53
上 传 者：
小陈3
说明： AD9361 IP核，Windows版本，Vivado2016.2
(AD9361 IP core, used on Windows, Vivado2016.2)
文件列表:
hdl-2016_r2 (0, 2017-07-19)
hdl-2016_r2\LICENSE (1914, 2017-07-19)
hdl-2016_r2\Makefile (1327, 2017-07-19)
hdl-2016_r2\library (0, 2017-07-19)
hdl-2016_r2\library\Makefile (4701, 2017-07-19)
hdl-2016_r2\library\altera (0, 2017-07-19)
hdl-2016_r2\library\altera\alt_serdes (0, 2017-07-19)
hdl-2016_r2\library\altera\alt_serdes\alt_serdes_hw.tcl (11664, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxcfg (0, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxcfg\avl_adxcfg.v (6798, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxcfg\avl_adxcfg_hw.tcl (2215, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxcvr (0, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxcvr\avl_adxcvr_hw.tcl (23403, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxphy (0, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxphy\avl_adxphy.v (41091, 2017-07-19)
hdl-2016_r2\library\altera\avl_adxphy\avl_adxphy_hw.tcl (6449, 2017-07-19)
hdl-2016_r2\library\altera\axi_adxcvr (0, 2017-07-19)
hdl-2016_r2\library\altera\axi_adxcvr\axi_adxcvr.v (5663, 2017-07-19)
hdl-2016_r2\library\altera\axi_adxcvr\axi_adxcvr_hw.tcl (3537, 2017-07-19)
hdl-2016_r2\library\altera\axi_adxcvr\axi_adxcvr_up.v (6264, 2017-07-19)
hdl-2016_r2\library\altera\common (0, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_cmos_clk.v (3242, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_cmos_in.v (4251, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_cmos_out.v (3728, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_cmos_out_core_c5.v (2965, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_dcfilter.v (3388, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_lvds_clk.v (3243, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_lvds_in.v (4311, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_lvds_out.v (4082, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_mul.v (3866, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_serdes_clk.v (7248, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_serdes_in.v (5694, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_serdes_in_core_c5.v (6154, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_serdes_out.v (4875, 2017-07-19)
hdl-2016_r2\library\altera\common\ad_serdes_out_core_c5.v (4745, 2017-07-19)
hdl-2016_r2\library\axi_ad6676 (0, 2017-07-19)
hdl-2016_r2\library\axi_ad6676\Makefile (1641, 2017-07-19)
... ...
# HDL Reference Designs
[Analog Devices Inc.] HDL libraries and projects
### Branches
Each release has its own branch and master always synced with the latest release.
To find out more information about the latest release please check the release notes.
Every branch, which has **dev** in its name, is a development branch and should handle it accordingly.
### [Latest Release Notes]
### [HDL User Guide]
### [HDL Help & Support]
[HDL User Guide]:http://wiki.analog.com/resources/fpga/docs/hdl
[HDL Help & Support]:http://ez.analog.com/community/fpga
[Latest Release Notes]:https://github.com/analogdevicesinc/hdl/releases
[Analog Devices Inc.]:http://www.analog.com/en/index.html
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