文件列表:

rd1183\docs (0, 2015-01-08)
rd1183\docs\rd1183.pdf (1356284, 2015-01-07)
rd1183\project (0, 2015-01-08)
rd1183\project\ecp5 (0, 2015-01-08)
rd1183\project\ecp5\verilog (0, 2015-01-08)
rd1183\project\ecp5\verilog\ecp5_verilog.ldf (2940, 2014-12-28)
rd1183\project\ecp5\verilog\ecp5_verilog.lpf (679, 2014-11-26)
rd1183\project\ecp5\verilog\ecp5_verilog.sty (13452, 2014-12-28)
rd1183\project\xo2 (0, 2015-01-08)
rd1183\project\xo2\verilog (0, 2015-01-08)
rd1183\project\xo2\verilog\xo2_verilog.ldf (2442, 2014-12-28)
rd1183\project\xo2\verilog\xo2_verilog.lpf (955, 2014-09-02)
rd1183\project\xo2\verilog\xo2_verilog.sty (13593, 2014-12-28)
rd1183\project\xo3l (0, 2015-01-08)
rd1183\project\xo3l\verilog (0, 2015-01-08)
rd1183\project\xo3l\verilog\xo3l_verilog.ldf (2642, 2014-12-28)
rd1183\project\xo3l\verilog\xo3l_verilog.lpf (955, 2014-09-02)
rd1183\project\xo3l\verilog\xo3l_verilog.sty (13596, 2014-12-28)
rd1183\simulation (0, 2015-01-08)
rd1183\simulation\ecp5 (0, 2015-01-08)
rd1183\simulation\ecp5\crc16_2lane.vo (22868, 2014-10-15)
rd1183\simulation\ecp5\packetheader_2s.vo (209968, 2014-10-15)
rd1183\simulation\ecp5\parallel2byte_10s_2s_43.vo (109320, 2014-10-15)
rd1183\simulation\ecp5\verilog (0, 2015-01-08)
rd1183\simulation\ecp5\verilog\rtl_verilog.do (1635, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog (0, 2015-01-08)
rd1183\simulation\ecp5\verilog\rtl_verilog\compilation.order (0, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\compile.cfg (1997, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\Edfmap.ini (19921, 2014-01-23)
rd1183\simulation\ecp5\verilog\rtl_verilog\library.cfg (193, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\moduleparser_command.log (305, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\projlib.cfg (162, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.adf (629, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.ado (4961, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.aws (181, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.sort (1396, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.spf (2582, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.tops (107, 2014-12-28)
rd1183\simulation\ecp5\verilog\rtl_verilog\rtl_verilog.wsp (6348, 2014-12-28)
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________________________________________________________________________ PARALLEL TO MIPI CSI2 Sensor Bridge Design Readme ------------------------------------------------------------------------- --------------------------------------------------------------------------- File List (50 files): --------------------------------------------------------------------------- 1. \rd1183\docs\rd1183_readme.txt --> read me file (this file) 2. \rd1183\docs\rd1183.pdf --> Parallel to MIPI CSI2 TX Bridge reference document 3. \rd1183\docs\revision_history.xlsx --> Revision History 4. \rd1183\source\verilog\xo2\crc16_2lane.ngo --> XO2 NGO file for crc16_2lane 5. \rd1183\source\verilog\xo2\packetheader_2s.ngo --> XO2 NGO file for packetheader 6. \rd1183\source\verilog\xo2\parallel2byte_10s_2s_43.ngo --> XO2 NGO file for parallel2byte 7. \rd1183\source\verilog\xo2\oddrx4.v --> XO2 source file for output DDR IO module 8. \rd1183\source\verilog\xo3l\crc16_2lane.ngo --> XO3L NGO file for crc16_2lane 9. \rd1183\source\verilog\xo3l\packetheader_2s.ngo --> XO3L NGO file for packetheader 10. \rd1183\source\verilog\xo3l\parallel2byte_10s_2s_43.ngo --> XO3L NGO file for parallel2byte 11. \rd1183\source\verilog\xo3l\oddrx4.v --> XO3L source file for output DDR IO module 12. \rd1183\source\verilog\ecp5\crc16_2lane.ngo --> ecp5 NGO file for crc16_2lane 13. \rd1183\source\verilog\ecp5\packetheader_2s.ngo --> ecp5 NGO file for packetheader 14. \rd1183\source\verilog\ecp5\parallel2byte_10s_2s_43.ngo --> ecp5 NGO file for parallel2byte 15. \rd1183\source\verilog\ecp5\oddrx4.v --> ecp5 source file for output DDR IO module 16. \rd1183\source\verilog\top.v --> Verilog source file for top module 17. \rd1183\source\verilog\byte_packetizer.v --> Verilog source file for byte_packetizer module 18. \rd1183\source\verilog\colorbar_gen.v --> Verilog source file for top module 19. \rd1183\source\verilog\compiler_directives.v --> Verilog source file for compiler_directives module 20. \rd1183\source\verilog\dphy_tx_inst.v --> Verilog source file for dphy_tx_inst module 21. \rd1183\source\verilog\io_controller_tx.v --> Verilog source file for io_controller_tx module 22. \rd1183\source\verilog\lp_hs_dly_ctrl.v --> Verilog source file for lp_hs_dly_ctrl module 23. \rd1183\source\verilog\top.v --> Verilog source file for top module 24. \rd1183\source\verilog\crc16_2lane_bb.v --> Verilog BlackBox file for NGO "crc16_2lane" 25. \rd1183\source\verilog\packetheader_bb.v --> Verilog BlackBox file for NGO "packetheader" 26. \rd1183\source\verilog\parallel2byte_bb.v --> Verilog BlackBox file for NGO "parallel2byte" 27. \rd1183\source\verilog\ipexpress\xo2\pll_pix2byte_RAW10_2lane.ipx --> XO2 IPExpress PLL file for clock generation 28. \rd1183\source\verilog\ipexpress\xo3L\pll_pix2byte_RAW10_2lane.ipx --> XO3L IPExpress PLL file for clock generation 29. \rd1183\source\verilog\ecp5\dphy_tx_inst --> Verilog source file for dphy_tx_inst module 30. \rd1183\source\verilog\ecp5\ gearing_converter_fifo --> Verilog source file for gearing_converter_fifo module 31. \rd1183\source\verilog\ecp5\ oddrx2 --> Verilog source file for oddrx2 module 32. \rd1183\source\verilog\ecp5\ oddrx4 --> Verilog source file for oddrx4 module 33. \rd1183\source\verilog\ecp5\pll_pix2byte_RAW10_2lane --> Verilog source file for pll_pix2byte_RAW10_2lane module 34. \rd1183\source\verilog\ecp5\pllx4 --> Verilog source file for pllx4 module 35. \rd1183\source\verilog\ecp5\top --> ecp5 Verilog source file for top module 36. \rd1183\testbench\verilog\Parallel2CSI2_tb_2lane.v --> TestBench for parallel to MIPI CSI2 TX design 37. \rd1183\project\xo2\verilog\xo2_verilog.ldf --> Diamond project file for XO2 MIPI csi2 tx design 38. \rd1183\project\xo3l\verilog\xo3l_verilog.ldf --> Diamond project file for XO3L MIPI csi2 tx design with synplifypro as synthesis tool 39. \rd1183\project\xo3l\verilog\ecp5_verilog.ldf --> Diamond project file for ecp5 MIPI csi2 tx design with LSE as synthesis tool 40. \rd1183\project\xo2\verilog\xo2_verilog.lpf --> constraint file for XO2 MIPI csi2 tx design 41. \rd1183\project\xo3l\verilog\xo3l_verilog.lpf --> constraint file for XO3L MIPI csi2 tx design with synplifypro as synthesis tool 42. \rd1183\project\xo3l\verilog\ecp5_verilog.lpf --> constraint file for ecp5 MIPI csi2 tx design with LSE as synthesis tool 43. \rd1183\project\xo2\verilog\xo2_verilog.sty --> strategy file for XO2 MIPI csi2 tx design 44. \rd1183\project\xo3l\verilog\xo3l_verilog.sty --> strategy file for XO3L MIPI csi2 tx design with synplifypro as synthesis tool 45. \rd1183\project\xo3l\verilog\ecp5_verilog.sty --> strategy file for ecp5 MIPI csi2 tx design with LSE as synthesis tool 46. \rd1183\simulation\xo3l\verilog\rtl_verilog.do --> functional simulation script file 47. . \rd1183\simulation\xo3l\verilog\timing_verilog.do --> timing simulation script file 48. \rd1183\simulation\xo2\crc16_2lane.vo --> netlist file for simulation 49. \rd1183\simulation\xo2\packetheader_2s.vo --> netlist file for simulation 50. \rd1183\simulation\xo2\parallel2byte_10s_2s_43.vo --> netlist file for simulation 51. \rd1183\simulation\ecp5\crc16_2lane.vo --> netlist file for simulation 52. \rd1183\simulation\ecp5\packetheader_2s.vo --> netlist file for simulation 53. \rd1183\simulation\ecp5\parallel2byte_10s_2s_43.vo --> netlist file for simulation 54. \rd1183\simulation\xo3l\crc16_2lane.vo --> netlist file for simulation 55. \rd1183\simulation\xo3l\packetheader_2s.vo --> netlist file for simulation 56. \rd1183\simulation\xo3l\parallel2byte_10s_2s_43.vo --> netlist file for simulation 57. \rd1183\simulation\xo2\verilog\simulation\simulation.spf --> script file for simulation 58. \rd1183\simulation\xo3l\verilog\rtlsim_syn\rtlsim_syn.spf --> script file for simulation 59. \rd1183\simulation\xo3l\verilog\rtlsim_lse\rtlsim_lse.spf --> script file for simulation --------------------------------------------------------------------------------------------------------------- Complier Directives\Parameters used: --------------------------------------------------------------------------------------------------------------- `define HS_1 >> Defines the number of HS (High Speed) Data Lanes; HS_3 = 4 lanes, HS_2 = 3 lanes, HS_1 = 2 lanes, HS_0 = 1 lanes `define LP_CLK >> Defines IO control for the LP (Low Power) Clock Lane `define LP_0 >> Defines IO control for the LP (Low Power) Data Lane 0 `define LP_1 >> Defines IO control for the LP (Low Power) Data Lane 1 `define LP_2 >> Defines IO control for the LP (Low Power) Data Lane 2 `define LP_3 >> Defines IO control for the LP (Low Power) Data Lane 3 `define sim >> Enable before generating verilog simulation files and also before simulating --------------------------------------------------------------------------------------------------------------- HOW TO OPEN A PROJECT IN DIAMOND: --------------------------------------------------------------------------------------------------------------- 1. Unzip the respective design files. 2. Launch Diamond and select "File -> Open -> Project..." 3. In the Open Project dialog, enter the Project location -- "\rd1183\project",select one device and then select one project. 4. Click Finish. Now the project is successfully loaded. --------------------------------------------------------------------------------------------------------------- HOW TO RUN PLACE AND ROUTE, JEDEC GENERATION, AND TIMING ANALYSIS IN DIAMOND: --------------------------------------------------------------------------------------------------------------- 1. Click the Process tab in the process panel of the Diamond dashboard. Double click on Place and Route Design. This will bring the design through synthesis, mapping, and place and route. 2. Click the Process tab in the process panel of the Diamond dashboard. a) MachXO2 , MachXO3L and ECP5 : Double click on "Export Files -> JEDEC File". This will generate the Jedec file for the design. 3. Once Place and Route is done, user can double click on Place and Route Trace Report on the right-side panel to get the timing analysis result. 4. For Timing simulation files , first enable the "`define sim " in the compiler_directives.v file. Double click on "Export Files -> verilog Simulation File". This will generate the VO and SDF files for the timing simulation of the design. ------------------------------------------------------------------------------------------------------- HOW TO RUN SIMULATION FROM DIAMOND: ------------------------------------------------------------------------------------------------------- There are two ways to bring up the Simulation: A. The simulation environment can be accessed by Script Files from Diamond: 1. Open compiler_directives.v file and uncomment "`define sim". 2. double clicking on the "XXXXXX.spf" script file in Lattice Diamond 3. Press SkiptoEnd button 4. Click Finish. This will bring up the Aldec simulator automatically. 5. Add the required signals into the Waveform panel 6. Run 100ns. 7. The simulation should end without error and a waveform similar to that indicated in document will be appeared in the waveform panel. (or) B. Starting the simulation from the Simulation Wizard in Diamond: 1. Open compiler_directives.v file and uncomment "`define sim". 2. Generate the verilog simulation file in the diamond project for the respective device. 3. Bring up the Simulation Wizard under the Tools menu 4. Next provide a name for simulation project, and select RTL simulation 5. Add the respective testbench file to the source file list. 6. Click Finish. This will bring up the Aldec simulator automatically. 7. In Aldec environment, you can manually activate the simulation or you can use a script 7.1 Use the provided script in the rd1183\simulation\ directory a. For functional simulation, change the PROJ_DIR to your local directory Address of the "simulation" b. For POST-ROUTE simulation, open the script and change the following: i) change the PROJ_DIR to your local directory Address of the "simulation" c. In Aldec , Click Tools > Execute Macro and select the xxx.do file to run the simulation d. This will run the simulation until 100us 7.2 You can manually activate the simulation a. Click Simulation > Initialize Simulation If prompted to select a top-level file, select the testbench as the top-level file and click Ok. b. Click File > New > Waveform, this will bring up the Waveform panel c. Click on the top-level testbench, drag all the signals into the Waveform panel d. Click Simulation > Run 100us. 8. The simulation should end without error and a waveform similar to that indicated in document will be appeared in the waveform panel. ---------------------------------------------------------------------------------------------------

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