FourToOneMux
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：27KB
下载次数：1
上传日期：2017-09-24 01:46:06
上 传 者：
Mood
说明： this is Implementation of 4 to 1 Multiplexer in verilog language for embedded design systems
文件列表:
lab#3 (0, 2016-04-21)
lab#3\lab_3.cr.mti (465, 2016-04-15)
lab#3\lab_3.mpf (13408, 2016-04-15)
lab#3\task_3.v (1008, 2016-04-13)
lab#3\test_task.v (1110, 2016-04-13)
lab#3\vsim.wlf (16384, 2016-04-13)
lab#3\work (0, 2016-04-21)
lab#3\work\@a@l@u (0, 2016-04-21)
lab#3\work\@a@l@u\verilog.asm (6126, 2016-04-13)
lab#3\work\@a@l@u\_primary.dat (415, 2016-04-13)
lab#3\work\@a@l@u\_primary.vhd (333, 2016-04-13)
lab#3\work\@a@l@u_@test (0, 2016-04-21)
lab#3\work\@a@l@u_@test\verilog.asm (6340, 2016-04-13)
lab#3\work\@a@l@u_@test\_primary.dat (632, 2016-04-13)
lab#3\work\@a@l@u_@test\_primary.vhd (76, 2016-04-13)
lab#3\work\counter4bit (0, 2016-04-21)
lab#3\work\counter4bit\verilog.asm (3275, 2016-04-13)
lab#3\work\counter4bit\_primary.dat (351, 2016-04-13)
lab#3\work\counter4bit\_primary.vhd (246, 2016-04-13)
lab#3\work\mux8to1 (0, 2016-04-21)
lab#3\work\mux8to1\verilog.asm (5182, 2016-03-31)
lab#3\work\mux8to1\_primary.dat (505, 2016-03-31)
lab#3\work\mux8to1\_primary.vhd (257, 2016-03-31)
lab#3\work\test_8to1 (0, 2016-04-21)
lab#3\work\test_8to1\verilog.asm (6130, 2016-03-31)
lab#3\work\test_8to1\_primary.dat (736, 2016-03-31)
lab#3\work\test_8to1\_primary.vhd (78, 2016-03-31)
lab#3\work\test_counter (0, 2016-04-21)
lab#3\work\test_counter\verilog.asm (5305, 2016-04-13)
lab#3\work\test_counter\_primary.dat (428, 2016-04-13)
lab#3\work\test_counter\_primary.vhd (84, 2016-04-13)
lab#3\work\_info (1006, 2016-04-13)
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