test59_TRIGU
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：254KB
下载次数：2
上传日期：2017-09-27 21:14:10
上 传 者：
uson
说明： VHDL
generating of trig signal
microsemi project
文件列表:
test59_TRIGU\component (0, 2017-07-02)
test59_TRIGU\component\work (0, 2017-09-11)
test59_TRIGU\component\work\DESIGN_FIRMWARE (0, 2017-09-11)
test59_TRIGU\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf (437, 2017-09-11)
test59_TRIGU\component\work\tb_top (0, 2017-09-11)
test59_TRIGU\component\work\tb_top\tb_top.cxf (1540, 2017-07-02)
test59_TRIGU\component\work\tb_top\tb_top.sdb (2082, 2017-09-11)
test59_TRIGU\component\work\tb_top\tb_top.vhd (2577, 2017-07-02)
test59_TRIGU\component\work\tb_top\tb_top_manifest.txt (320, 2017-07-02)
test59_TRIGU\constraint (0, 2017-07-01)
test59_TRIGU\coreconsole (0, 2017-07-01)
test59_TRIGU\designer (0, 2017-07-01)
test59_TRIGU\designer\impl1 (0, 2017-07-02)
test59_TRIGU\designer\impl1\designer_synth_check.log (1198, 2017-07-02)
test59_TRIGU\designer\impl1\simulation (0, 2017-07-01)
test59_TRIGU\designer\impl1\TRIGU.ide_des (181, 2017-07-02)
test59_TRIGU\designer\impl1\TRIGU.tcl (1489, 2017-07-02)
test59_TRIGU\hdl (0, 2017-07-02)
test59_TRIGU\hdl\TRIGU.vhd (1165, 2017-07-02)
test59_TRIGU\simulation (0, 2017-09-11)
test59_TRIGU\simulation\modelsim.ini (301, 2017-09-11)
test59_TRIGU\simulation\modelsim.ini.sav (301, 2017-07-02)
test59_TRIGU\simulation\postsynth (0, 2017-09-11)
test59_TRIGU\simulation\postsynth\_info (2087, 2017-09-11)
test59_TRIGU\simulation\postsynth\_lib.qdb (49152, 2017-09-11)
test59_TRIGU\simulation\postsynth\_lib1_0.qdb (32768, 2017-09-11)
test59_TRIGU\simulation\postsynth\_lib1_0.qpg (8192, 2017-09-11)
test59_TRIGU\simulation\postsynth\_lib1_0.qtl (55846, 2017-09-11)
test59_TRIGU\simulation\postsynth\_vmake (29, 2017-09-11)
test59_TRIGU\simulation\run.do (708, 2017-09-11)
test59_TRIGU\simulation\tb_top_postsynth_simulation.log (3331, 2017-09-11)
test59_TRIGU\simulation\vsim.wlf (73728, 2017-09-11)
test59_TRIGU\smartgen (0, 2017-09-11)
test59_TRIGU\smartgen\DESIGN_FIRMWARE_work.ixf (443, 2017-09-11)
test59_TRIGU\smartgen\smartgen.aws (434, 2017-09-11)
test59_TRIGU\smartgen\tb_top_work.ixf (604, 2017-07-02)
test59_TRIGU\stimulus (0, 2017-07-02)
test59_TRIGU\stimulus\tb_clk.vhd (1316, 2017-07-02)
test59_TRIGU\synthesis (0, 2017-07-02)
test59_TRIGU\synthesis\.recordref (0, 2017-07-02)
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