test51_PLL
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：292KB
下载次数：1
上传日期：2017-09-27 21:19:12
上 传 者：
uson
说明： VHDL
How to use PLL-IP core
microsemi project
文件列表:
test51_PLL\component (0, 2017-06-08)
test51_PLL\component\work (0, 2017-06-08)
test51_PLL\component\work\DESIGN_FIRMWARE (0, 2017-06-08)
test51_PLL\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf (437, 2017-06-08)
test51_PLL\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.sdb (896, 2017-06-08)
test51_PLL\component\work\DESIGN_IO (0, 2017-06-08)
test51_PLL\component\work\DESIGN_IO\DESIGN_IO.cxf (413, 2017-06-08)
test51_PLL\component\work\DESIGN_IO\DESIGN_IO.sdb (1352, 2017-06-08)
test51_PLL\component\work\tb_top (0, 2017-06-08)
test51_PLL\component\work\tb_top\tb_top.cxf (1835, 2017-06-08)
test51_PLL\component\work\tb_top\tb_top.sdb (2147, 2017-06-08)
test51_PLL\component\work\tb_top\tb_top.vhd (2790, 2017-06-08)
test51_PLL\component\work\tb_top\tb_top_manifest.txt (316, 2017-06-08)
test51_PLL\component\work\top (0, 2017-06-08)
test51_PLL\component\work\top\datasheet.xsl (34989, 2017-06-08)
test51_PLL\component\work\top\top.cxf (1523, 2017-06-08)
test51_PLL\component\work\top\top.sdb (2793, 2017-06-08)
test51_PLL\component\work\top\top_DataSheet.xml (1714, 2017-06-08)
test51_PLL\constraint (0, 2017-06-08)
test51_PLL\coreconsole (0, 2017-06-08)
test51_PLL\designer (0, 2017-06-08)
test51_PLL\designer\impl1 (0, 2017-06-08)
test51_PLL\designer\impl1\designer_synth_check.log (1182, 2017-06-08)
test51_PLL\designer\impl1\simulation (0, 2017-06-08)
test51_PLL\designer\impl1\top.ide_des (177, 2017-06-08)
test51_PLL\designer\impl1\top.tcl (1473, 2017-06-08)
test51_PLL\firmware (0, 2017-06-08)
test51_PLL\hdl (0, 2017-06-08)
test51_PLL\simulation (0, 2017-06-08)
test51_PLL\simulation\modelsim.ini (301, 2017-06-08)
test51_PLL\simulation\postsynth (0, 2017-06-08)
test51_PLL\simulation\postsynth\_info (2300, 2017-06-08)
test51_PLL\simulation\postsynth\_lib.qdb (49152, 2017-06-08)
test51_PLL\simulation\postsynth\_lib1_0.qdb (32768, 2017-06-08)
test51_PLL\simulation\postsynth\_lib1_0.qpg (32768, 2017-06-08)
test51_PLL\simulation\postsynth\_lib1_0.qtl (36210, 2017-06-08)
test51_PLL\simulation\postsynth\_vmake (29, 2017-06-08)
test51_PLL\simulation\run.do (704, 2017-06-08)
test51_PLL\simulation\tb_top_postsynth_simulation.log (3402, 2017-06-08)
test51_PLL\simulation\vsim.wlf (81920, 2017-06-08)
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