CV_FPGA_to_HPS_Bridge_Design_Example
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：1787KB
下载次数：26
上传日期：2017-09-28 13:13:11
上 传 者：
雨亦清流
说明： FPGA通过AXI总线传输数据给ARM,ARM使用DMA方式接收数据！
(FPGA to ARM Bridge design example)
文件列表:
CV_FPGA_to_HPS_Bridge_Design_Example (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\CV_fpga_to_hps_bridge.qpf (1359, 2016-07-27)
CV_FPGA_to_HPS_Bridge_Design_Example\CV_fpga_to_hps_bridge.qsf (51785, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\CV_fpga_to_hps_bridge_top.v (8510, 2016-07-27)
CV_FPGA_to_HPS_Bridge_Design_Example\DMA_system.qsys (26940, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\doc (0, 2016-09-27)
CV_FPGA_to_HPS_Bridge_Design_Example\doc\sample_output.txt (3401, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\doc\throughput_results.xlsx (12230, 2016-09-27)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\alt_types.h (2146, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\emif.xml (9961, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\hps.xml (13463, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\hps_system_cycloneV_hps.hiof (2701, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\id (100, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sdram_io.h (2870, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sequencer.c (333560, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sequencer.h (24219, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sequencer_auto.h (10660, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sequencer_auto_ac_init.c (2201, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sequencer_auto_inst_init.c (2904, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\sequencer_defines.h (5643, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\system.h (1947, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\tclrpt.c (41644, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_isw_handoff\hps_system_cycloneV_hps\tclrpt.h (17753, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_system.qsys (54452, 2016-08-20)
CV_FPGA_to_HPS_Bridge_Design_Example\hps_system.sopcinfo (3148640, 2016-08-20)
CV_FPGA_to_HPS_Bridge_Design_Example\ip (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\axi_cache_secruity_bridge (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\axi_cache_secruity_bridge\axi_cache_secruity_bridge.v (16508, 2016-04-19)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\axi_cache_secruity_bridge\AXI_cache_secruity_bridge_hw.tcl (13075, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\prbs_pattern_checker (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\prbs_pattern_checker\mtm_prbs_pattern_checker.v (21387, 2016-04-19)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\prbs_pattern_checker\prbs_pattern_checker_hw.tcl (9910, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\prbs_pattern_generator (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\prbs_pattern_generator\mtm_prbs_pattern_generator.v (17754, 2016-04-19)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\prbs_pattern_generator\prbs_pattern_generator_hw.tcl (9955, 2016-07-28)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\reset_synchronizer (0, 2016-09-24)
CV_FPGA_to_HPS_Bridge_Design_Example\ip\reset_synchronizer\custom_reset_synchronizer_hw.tcl (10250, 2016-07-28)
... ...
FPGA-to-HPS Bridge Design Example for CV SoC DevKit Rev E
=========================================================
Requirements
-----------------------
* CV Soc DevKit Rev E (some older versions may also work)
* Quartus II 16.0b211
* SoC EDS 16.0b211
Note that U-Boot can only be compiled on a Linux host machine
Contents
-----------------------
CV_FPGA_to_HPS_Bridge_Design_Example
output_files
CV_fpga_to_hps_bridge.sof - prebuilt FPGA configuration file
software
Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU - HPS baremetal software project
spl_bsp - prebuilt Preloader
doc
readme.txt - this file
sample_output.txt - sample results
throughput_results.xlsx - spreadsheet with results
CV_fpga_to_hps_bridge.qpf - hardware project
...
Running Instructions
-----------------------
1. Extract the archive on a folder on the host PC
2. Use Quartus Programmer to program FPGA with output_files/CV_fpga_to_hps_bridge.sof
3. Start Eclipse from Embedded Command Shell
4. Select workspace to be anywhere on your computer
5. Import the software/Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU project in Eclipse. Do not select the option to copy the files into the current workspace
6. Build the project
7. Run the project from Eclipse.
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