code

所属分类:其他
开发工具:Verilog
文件大小:1262KB
下载次数:13
上传日期:2017-10-01 23:34:56
上 传 者ashokpamarthy
说明:  Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage.

文件列表:
code\adder.v (808, 2017-10-01)
code\code .exe (3292672, 2014-02-20)
code\comp.v (983, 2017-10-01)
code\compressor.docx (579198, 2017-10-01)
code\compressor.v (655, 2017-10-01)
code\fa.v (629, 2017-10-01)
code\ha.v (605, 2017-10-01)
code\multipler.v (1611, 2017-10-01)
code\multipler8.txt (4410, 2017-10-01)
code\multipler8.v (4590, 2017-10-01)
code\multipler8x8.v (4405, 2017-10-01)
code\mux.v (587, 2017-10-01)
code\rca15.v (1106, 2017-10-01)
code\xor1.v (579, 2017-10-01)
code (0, 2017-10-01)

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