bist 2017 paper
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:1532KB
下载次数:8
上传日期:2017-10-05 13:00:49
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Maddy619
说明: A new low-power (LP) scan-based built-in selftest
(BIST) technique is proposed based on weighted pseudorandom
test pattern generation and reseeding. A new LP scan
architecture is proposed, which supports both pseudorandom
testing and deterministic BIST. During the pseudorandom testing
phase, an LP weighted random test pattern generation scheme
is proposed by disabling a part of scan chains.
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bist 2017 paper.pdf (2078899, 2017-09-16)
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