new

所属分类:其他
开发工具:Verilog
文件大小:6KB
下载次数:2
上传日期:2017-10-19 09:44:13
上 传 者Animal
说明:  1、PC和寄存器组使用时钟触发。 2、指令存储器和数据存储器存储单元宽度一律使用8位,即一个字节的存储单位。 3、控制器部分可以考虑用控制信号真值表方法(有共性部分)与用case语句方法逐个产生各指令其它控制信号相配合,注意:信号必须与状态配合。。当然,还可以用其它方法,自己考虑。 4、试用的汇编程序,而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况:“小于”和“大于等于”;beq、bne指令必须检查两种情况:“等”和“不等”。这段汇编程序必须尽量优化,同时,给出每条指令在内存中的地址。
(1, PC and register groups are clocked. 2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit. 3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own. 4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)

文件列表:
new\ALU.v (1042, 2017-05-31)
new\ControlUnit.v (3727, 2017-06-02)
new\CPU.v (2124, 2017-05-31)
new\DataMemory.v (635, 2017-05-27)
new\DR.v (137, 2017-05-27)
new\Extend.v (253, 2017-06-02)
new\InstructionMemory.v (422, 2017-05-27)
new\IR.v (291, 2017-05-27)
new\Mux_32.v (180, 2017-05-27)
new\Mux_PCSrc.v (636, 2017-05-27)
new\Mux_RegDst.v (471, 2017-05-27)
new\PC.v (451, 2017-05-27)
new\Regfile.v (638, 2017-05-31)
new\test.v (1507, 2017-05-27)
new (0, 2017-06-04)

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