文件列表:

Altera (0, 2017-10-30)
Altera\.qsys_edit (0, 2017-10-30)
Altera\.qsys_edit\EDAC_SDRAM_Controller_Demo.xml (82896, 2017-10-30)
Altera\.qsys_edit\filters.xml (66, 2017-10-30)
Altera\.qsys_edit\preferences.xml (568, 2017-10-30)
Altera\EDAC_SDRAM_Controller.qpf (1318, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo.ipregen.rpt (2308, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo.qsf (12974, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo.qws (722, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo.tcl (14384, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo (0, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo.bsf (10224, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo.xml (590867, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo_bb.v (1243, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo_generation.rpt (9403, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo_generation_previous.rpt (9403, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo_inst.v (2514, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\EDAC_SDRAM_Controller_Demo_inst.vhd (5088, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis (0, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\EDAC_SDRAM_Controller_Demo.vhd (55933, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\edac_sdram_controller_demo_rst_controller.vhd (9123, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\edac_sdram_controller_demo_rst_controller_001.vhd (9184, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules (0, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_altpll_0.v (11689, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_mm_interconnect_0.v (19604, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_mm_interconnect_1.v (171131, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_mm_interconnect_1_avalon_st_adapter.v (6212, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0.v (5830, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu.v (196092, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_debug_slave_sysclk.v (6502, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_debug_slave_tck.v (8899, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_debug_slave_wrapper.v (10460, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_mult_cell.v (8259, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_nios2_gen2_0_cpu_test_bench.v (29081, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\EDAC_SDRAM_Controller_Demo_onchip_memory2_0.v (4882, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\IOBUF.vhd (6080, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\OBUF.vhd (5166, 2017-10-30)
Altera\EDAC_SDRAM_Controller_Demo\synthesis\submodules\SPISlaveToAvalonMasterBridge.v (85753, 2017-10-30)
... ...

# EDAC SDRAM Controller This repository hosts the developed code that implements the proposed SEU mitigation technique presented in: _E.Kyriakakis, K. Ngo and J.Oberg, "Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller", In proceeedings of NORCAS-2017, Linkoping, Sweden._ ## Structure * Altera: hosts a demo project that implements the controller on a Cyclone IV DE2-115 target board * Xilinx: hosts a demo project that implements the controller for an Artix-7 200T FPGA * ModelSim: hosts wave configurations for easier simulation * blaze_src: hosts demo software project for the MicroBlaze soft-core processor that evaluates the functionality of the SDRAM Controller * nios2_src: hosts demo software project for the NIOSII soft-core processor that evaluates the functionality of the SDRAM Controller * controller_src: is the main VHDL codebase for the developed controller component * other_src: is a VHDL codebase for any other developed components used in the demo projects

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