文件列表:

xapp502\bitformat.pl (3842, 2001-10-10)
xapp502\SelectMAP.c (12528, 2009-04-16)
xapp502\SelectMAP.v (5974, 2009-04-16)
xapp502\SelectMAP.vhd (6199, 2009-04-16)
xapp502\SlaveSerial.c (12036, 2009-04-16)
xapp502\SlaveSerial.v (5173, 2009-04-16)
xapp502\SlaveSerial.vhd (5539, 2009-04-16)
xapp502 (0, 2012-10-29)

******************************************************************************* ** 2001-2009 Xilinx, Inc. All Rights Reserved. ** Confidential and proprietary information of Xilinx, Inc. ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 2.0.1 ** \ \ Filename: ** / / Date Last Modified: 04/16/2009 ** /___/ /\ Date Created: 11/15/2001 ** \ \ / \ ** \___\/\___\ ** ** Device: Spartan and Virtex FPGA families (except Spartan/Spartan-XL) ** Purpose: Configure a FPGA from an embedded processor. ** Reference: http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf ** Revision History: ** 11/01/2001 - Created ** 12/06/2007 - Added extra CCLK pulses to ensure DONE=High and reach ** end-of-startup in the presence of startup-extending ** bitgen options such as -g LCK_cycle or -g Match_cycle. ** See the FPGA user guides for startup information. ** 04/16/2009 - Fixed illegal reg declarations to wire declarations in ** Verilog files. Updated headers in .v and .vhd files. ******************************************************************************* ** ** ** Disclaimer: ** ** This disclaimer is not a license and does not grant any rights to the materials ** distributed herewith. Except as otherwise provided in a valid license issued to you ** by Xilinx, and to the maximum extent permitted by applicable law: ** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, ** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, ** INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR ** FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract ** or tort, including negligence, or under any other theory of liability) for any loss or damage ** of any kind or nature related to, arising under or in connection with these materials, ** including for any direct, or any indirect, special, incidental, or consequential loss ** or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered ** as a result of any action brought by a third party) even if such damage or loss was ** reasonably foreseeable or Xilinx had been advised of the possibility of the same. ** Critical Applications: ** ** Xilinx products are not designed or intended to be fail-safe, or for use in any application ** requiring fail-safe performance, such as life-support or safety devices or systems, ** Class III medical devices, nuclear facilities, applications related to the deployment of airbags, ** or any other applications that could lead to death, personal injury, or severe property or ** environmental damage (individually and collectively, "Critical Applications"). Customer assumes ** the sole risk and liability of any use of Xilinx products in Critical Applications, subject only ** to applicable laws and regulations governing limitations on product liability. ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ******************************************************************************* See XAPP502 for the use of the following files that are included in xapp502.zip: bitformat.readme - readme file for the bitformat.pl perl script bitformat.pl - perl script to parse bitstream SelectMAP.c - C code for SelectMAP download SelectMAP.v - Verilog code for SelectMAP CPLD design SelectMAP.vhd - VHDL code for SelectMAP CPLD design SlaveSerial.c - C code for Slave Serial download SlaveSerial.v - Verilog code for Slave Serial CPLD design SlaveSerial.vhd - VHDL code for Slave Serial CPLD design

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