文件列表:

multiboot_address_table\multiboot_address_table.tcl (17861, 2015-04-16)
multiboot_address_table\timer1.bin (1024, 2015-04-16)
multiboot_address_table\timer2.bin (60, 2015-04-16)
ready_to_download\bitstreams (0, 2015-06-18)
ready_to_download\bitstreams\Top_MultiBoot_Module_A.bit (1020489, 2015-04-13)
ready_to_download\bitstreams\Top_MultiBoot_Module_B.bit (1016249, 2015-04-13)
ready_to_download\bitstreams\Top_MultiBoot_Module_B_corrupted.bit (1016249, 2015-04-14)
ready_to_download\kc705_golden_corrutped_multiboot.mcs (5728154, 2015-04-14)
ready_to_download\kc705_golden_multiboot.mcs (5728154, 2015-04-14)
tcl\script (0, 2015-06-18)
tcl\script\create_design.tcl (1418, 2015-04-13)
tcl\script\design.xdc (1707, 2015-04-13)
tcl\sources (0, 2015-06-18)
tcl\sources\Golden (0, 2015-06-18)
tcl\sources\Golden\Golden_top.vhd (1357, 2015-04-14)
tcl\sources\Golden\LED_Display.vhd (1368, 2015-04-13)
tcl\sources\Update (0, 2015-06-18)
tcl\sources\Update\LED_Display.vhd (1380, 2015-04-13)
tcl\sources\Update\Update_top.vhd (1343, 2015-04-14)
Vivado\Golden (0, 2015-06-18)
Vivado\Golden\Golden.cache (0, 2015-06-18)
Vivado\Golden\Golden.cache\compile_simlib (0, 2015-04-13)
Vivado\Golden\Golden.cache\wt (0, 2015-06-18)
Vivado\Golden\Golden.cache\wt\java_command_handlers.wdf (658, 2015-06-18)
Vivado\Golden\Golden.cache\wt\synthesis.wdf (3749, 2015-06-18)
Vivado\Golden\Golden.cache\wt\synthesis_details.wdf (97, 2015-06-18)
Vivado\Golden\Golden.cache\wt\webtalk_pa.xml (1445, 2015-06-18)
Vivado\Golden\Golden.hw (0, 2015-06-18)
Vivado\Golden\Golden.hw\Golden.lpr (284, 2015-06-18)
Vivado\Golden\Golden.runs (0, 2015-06-18)
Vivado\Golden\Golden.runs\.jobs (0, 2015-06-18)
Vivado\Golden\Golden.runs\.jobs\vrs_config_1.xml (557, 2015-04-13)
Vivado\Golden\Golden.runs\.jobs\vrs_config_10.xml (557, 2015-04-13)
Vivado\Golden\Golden.runs\.jobs\vrs_config_11.xml (301, 2015-04-13)
Vivado\Golden\Golden.runs\.jobs\vrs_config_12.xml (277, 2015-06-18)
Vivado\Golden\Golden.runs\.jobs\vrs_config_13.xml (759, 2015-06-18)
Vivado\Golden\Golden.runs\.jobs\vrs_config_2.xml (306, 2015-04-13)
Vivado\Golden\Golden.runs\.jobs\vrs_config_3.xml (557, 2015-04-13)
Vivado\Golden\Golden.runs\.jobs\vrs_config_4.xml (298, 2015-04-13)
... ...

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2015 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 1.0.0 Date Last Modified: 19April2015 Date Created: 19April2015 Associated Filename: xapp1247.zip Associated Document: XAPP1247, MultiBoot with 7Series FPGAs using SPI Interface Supported Device(s): 7Series ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 19April2015 1.0 Initial Xilinx release. ========================================================================= 2. OVERVIEW This readme describes how to use the files that come with XAPP1247. The MultiBoot design runs on KC705 demo kit. The reference system contains two software projects: Golden Update/MultiBoot ready_to_download directory contain flash programming files for quick demo on KC705. Bitstream folder in the same directory contains .bit files used to generate .mcs files. VIVADO directory contains the compiled projects for Golden and Update design runs. tcl dirctory contains source files and tcl script to build the projects in non project mode. multiboot_address_table directory contains tcl script to generate Barrier images along with address map locations of images in flash memory device. 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * Xilinx Vivado Design Suite 2015.1 4. DESIGN FILE HIERARCHY \readme.txt | This file \ready_to_download | This folder contains ready to download .mcs files for a quick | demo. \vivado | This folder contains compliled Golden and Udpate designs | using Vivado 2015.1 for reference \tcl | This folder contains tcl script and source files to generate Golden | and Update bitstreams in Non-project mode. | To run the tcl script, unzip the reference design folder. | Open a Vivado Tcl Shell: | Start -> All Programs -> Xilinx Design Tools -> Vivado 2015.1 -> Vivado 2015.1 Tcl Shell | In Vivado Tcl Shell type: | > cd C:/xapp1247/tcl/script | > source create_design.tcl | Follow the instructions provided in the application note for information | how to setup, and run the design on board. \multiboot_address_table | This folder contains multiboot_address_table.tcl script to generate barrier/timer | images. For insturcitons how to use this script refer to Advanced section of xapp1247. 5. SUPPORT To obtain technical support for this reference design, go to www.xilinx.com/support to locate answers to known issues in the Xilinx Answers Database or to create a WebCase.

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