Verilog_Ip_PLL
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：6228KB
下载次数：4
上传日期：2017-11-15 17:06:02
上 传 者：
ET@AF
说明： 使用verilog 硬件描述语言编写的PLL调用程序，希望对大家有帮助！
(Using Verilog hardware description language written in the PLL call program, I hope to help you!)
文件列表:
Verilog_Ip_PLL\db\.cmp.kpt (211, 2016-04-19)
Verilog_Ip_PLL\db\altsyncram_qt14.tdf (7504, 2016-03-23)
Verilog_Ip_PLL\db\cmpr_ngc.tdf (1684, 2016-03-23)
Verilog_Ip_PLL\db\cmpr_rgc.tdf (2006, 2016-03-23)
Verilog_Ip_PLL\db\cntr_23j.tdf (3298, 2016-03-23)
Verilog_Ip_PLL\db\cntr_egi.tdf (3864, 2016-03-23)
Verilog_Ip_PLL\db\cntr_g9j.tdf (4102, 2016-03-23)
Verilog_Ip_PLL\db\decode_dvf.tdf (1565, 2016-03-23)
Verilog_Ip_PLL\db\logic_util_heursitic.dat (41712, 2016-04-19)
Verilog_Ip_PLL\db\mux_rsc.tdf (4725, 2016-03-23)
Verilog_Ip_PLL\db\PLL_altpll.v (4322, 2016-03-23)
Verilog_Ip_PLL\db\prev_cmp_Verilog_Ip_PLL.qmsg (95425, 2016-03-23)
Verilog_Ip_PLL\db\stp1_auto_stripped.stp (6825, 2017-10-11)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(0).cnf.cdb (979, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(0).cnf.hdb (751, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(1).cnf.cdb (1985, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(1).cnf.hdb (1262, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(10).cnf.cdb (2064, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(10).cnf.hdb (744, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(100).cnf.cdb (1371, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(100).cnf.hdb (750, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(101).cnf.cdb (1302, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(101).cnf.hdb (753, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(102).cnf.cdb (1775, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(102).cnf.hdb (1078, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(103).cnf.cdb (4317, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(103).cnf.hdb (1229, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(104).cnf.cdb (4317, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(104).cnf.hdb (1214, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(105).cnf.cdb (1500, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(105).cnf.hdb (756, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(106).cnf.cdb (1372, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(106).cnf.hdb (750, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(107).cnf.cdb (1302, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(107).cnf.hdb (753, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(108).cnf.cdb (4368, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(108).cnf.hdb (2474, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(109).cnf.cdb (13818, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(109).cnf.hdb (3582, 2016-03-23)
Verilog_Ip_PLL\db\Verilog_Ip_PLL.(11).cnf.cdb (1489, 2016-03-23)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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