LAB18
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：213KB
下载次数：4
上传日期：2011-04-29 02:24:40
上 传 者：
jack 998
说明： 学校最新试验箱配套历程，这是最后一个实验
(New chamber supporting the school history, this is the last experiment)
文件列表:
LAB18\BIN2GARY.bsf (1799, 2007-04-15)
LAB18\BIN2GRAY.v (676, 2007-04-15)
LAB18\db\design.(0).cnf.cdb (733, 2008-11-28)
LAB18\db\design.(0).cnf.hdb (534, 2008-11-28)
LAB18\db\design.(1).cnf.cdb (852, 2008-11-28)
LAB18\db\design.(1).cnf.hdb (464, 2008-11-28)
LAB18\db\design.asm.qmsg (2178, 2008-11-28)
LAB18\db\design.asm_labs.ddb (12182, 2008-11-28)
LAB18\db\design.cbx.xml (88, 2008-11-28)
LAB18\db\design.cmp.cdb (2705, 2008-11-28)
LAB18\db\design.cmp.hdb (6782, 2008-11-28)
LAB18\db\design.cmp.logdb (4, 2008-11-28)
LAB18\db\design.cmp.rdb (16422, 2008-11-28)
LAB18\db\design.cmp.tdb (1791, 2008-11-28)
LAB18\db\design.cmp0.ddb (48774, 2008-11-28)
LAB18\db\design.cmp2.ddb (40172, 2008-11-28)
LAB18\db\design.db_info (137, 2008-11-28)
LAB18\db\design.eco.cdb (161, 2008-11-28)
LAB18\db\design.fit.qmsg (13385, 2008-11-28)
LAB18\db\design.hier_info (894, 2008-11-28)
LAB18\db\design.hif (1056, 2008-11-28)
LAB18\db\design.map.cdb (1115, 2008-11-28)
LAB18\db\design.map.hdb (6616, 2008-11-28)
LAB18\db\design.map.logdb (4, 2008-11-28)
LAB18\db\design.map.qmsg (4007, 2008-11-28)
LAB18\db\design.pre_map.cdb (1016, 2008-11-28)
LAB18\db\design.pre_map.hdb (7136, 2008-11-28)
LAB18\db\design.rtlv.hdb (7131, 2008-11-28)
LAB18\db\design.rtlv_sg.cdb (1183, 2008-11-28)
LAB18\db\design.rtlv_sg_swap.cdb (522, 2008-11-28)
LAB18\db\design.sgdiff.cdb (858, 2008-11-28)
LAB18\db\design.sgdiff.hdb (7138, 2008-11-28)
LAB18\db\design.signalprobe.cdb (881, 2008-11-28)
LAB18\db\design.sim.vwf (6762, 2007-04-15)
LAB18\db\design.sld_design_entry.sci (154, 2008-11-28)
LAB18\db\design.sld_design_entry_dsc.sci (154, 2008-11-28)
LAB18\db\design.syn_hier_info (0, 2008-11-28)
LAB18\db\design.tan.qmsg (4977, 2008-11-28)
LAB18\db\design.tis_db_list.ddb (174, 2008-11-28)
LAB18\db\design.tmw_info (159, 2008-11-28)
... ...
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