文件列表:

Forwarding (0, 2014-09-29)
Forwarding\Core.v (15805, 2014-09-29)
Forwarding\Core_TB.v (3278, 2014-09-29)
Forwarding\DMem.v (5598, 2014-09-29)
Forwarding\IMem.v (5594, 2014-09-29)
Forwarding\reg_bank.v (1415, 2014-09-29)
LICENSE.txt (1099, 2014-09-29)
Pipeline (0, 2014-09-29)
Pipeline\Core.v (12003, 2014-09-29)
Pipeline\Core_TB .v (2362, 2014-09-29)
Pipeline\DMem.v (5598, 2014-09-29)
Pipeline\IMem.v (5594, 2014-09-29)
Pipeline\reg_bank.v (1089, 2014-09-29)
Single-Cycle (0, 2014-09-29)
Single-Cycle\Core.v (10460, 2014-09-29)
Single-Cycle\Core_TB.v (779, 2014-09-29)
Single-Cycle\DMem.v (5598, 2014-09-29)
Single-Cycle\IMem.v (5594, 2014-09-29)
Single-Cycle\reg_bank.v (1305, 2014-09-29)
Test Cases (0, 2014-09-29)
Test Cases\AndThenJR_TestCase.coe (233, 2014-09-29)
Test Cases\And_TestCase.coe (200, 2014-09-29)
Test Cases\BEQ_TestCase.coe (233, 2014-09-29)
Test Cases\Jump_TestCase.coe (97, 2014-09-29)
Test Cases\Load_in_Reg.coe (98, 2014-09-29)
Test Cases\Or_TestCase.coe (234, 2014-09-29)
Test Cases\Pipeline1.coe (229, 2014-09-29)
Test Cases\Pipeline2.coe (199, 2014-09-29)
Test Cases\Pipeline3.coe (335, 2014-09-29)
Test Cases\Pipeline_TestCase.coe (541, 2014-09-29)
Test Cases\SLL_TestCase.coe (200, 2014-09-29)
Test Cases\lwsw.coe (677, 2014-09-29)
Test Cases\pipeline_Add_TestCase.coe (263, 2014-09-29)
forwarding-1.gif (86782, 2014-09-29)
forwarding-2.gif (65952, 2014-09-29)

MIPS R3000 Verilog Code ======================= MIPS R3000 processor verilog code to be synthesized on Spartan 3E FPGA board.

This project consists of 4 Parts :

• Single Cycle Processor
• Multi Cycle Pipelined Processor (Without Forwarding)
• Hazard Free Multi Cycle Processor (With Forwarding)
• .coe TestCases

In order to run this project, you might need to regenerate memories for Instruction and Data Memory using IPCore in Xilinx ISE Tools. You can then load the coe files in your Instruction memory.

Single Cycle Processor

This part lacks unaligned load in memory and lh sh instructions.

Multi Cycle Processor

This part lacks jump instructions and lh, sh and unaligned load.

Multi Cycle with Forwarding Processor

This part lacks jump instructions and lh, sh and unaligned load.

Pipeline & Forwardings

 

Core.v

This file consists of the main parts of our processor. Instruction Fetch is done using the generated Instruction Memory. Instruction Decode is done using an always loop, Control Unit is also implemented as an always block, ALU has another always block on its own. The forwarding multiplexers and forwarding unit has another always block.

Core_TB.v

This file is our testbench, it instantiates Core.v and generates clock and nrst signal in order for our Core module to work. You can then monitor the processor's behavior using either ISim or Modelsim.

reg_bank.v

This module is our register bank which reads asynchronously and writes on negative clk edge. We have modified our register banks to read on the clk edge for our pipelined versions.

IMem.v

This module is generated by IPCore Generator and is our Instruction memory. (Size: 32x***)

DMem.v

This module is generated by IPCore Generator and is our Data memory. We instantiate it four times in our Core module. (Size: 8x***)

*.coe

These are our instructions that will be loaded in Instruction Memory to be executed.

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