ethernet_loopback
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：23381KB
下载次数：41
上传日期：2017-11-20 10:21:38
上 传 者：
marktuwen
说明： 通过FPGA驱动千兆以太网口，完成SPARTAN6上的UDP数据包闭环测试，即通过网口发送数据包到FPGA，FPGA内部将接收到的数据返回到PC机，建议测试之前添加ARP静态绑定，FGPA内部的IP以及MAC地址在ROM里的COE文档里可以看到，发送端添加了CRC以及整体CHECKSUM的计算
(Driven by FPGA Gigabit Ethernet port, UDP SPARTAN6 data packet on the closed loop test, through the network to send data packets to FPGA, FPGA will receive the data back to the PC, the proposed test before adding ARP static binding, FGPA internal IP and MAC address in the COE document in the ROM where you can see, the sender adds CRC and CHECKSUM integral calculation)
文件列表:
20171017.cfi (480, 2017-10-17)
20171017.mcs (4084021, 2017-10-17)
20171017.prm (712, 2017-10-17)
checksum.fdo (1317, 2015-11-21)
checksum.udo (381, 2015-11-21)
checksum_summary.html (3898, 2015-09-16)
checksum_wave.fdo (426, 2015-11-21)
crc_envsettings.html (10185, 2015-09-16)
crc_summary.html (3997, 2015-09-16)
ethernet_loopback.cfi (489, 2015-11-20)
ethernet_loopback.mcs (4084021, 2015-11-20)
ethernet_loopback.prm (730, 2015-11-20)
ethernet_send.cfi (460, 2015-08-18)
ethernet_send.gise (20193, 2017-10-17)
ethernet_send.prm (672, 2015-08-18)
ethernet_send.xise (40671, 2017-10-17)
header_ram.coe (314, 2015-11-20)
ipcore_dir (0, 2017-10-17)
ipcore_dir\coregen.cgp (238, 2015-11-09)
ipcore_dir\coregen.log (2977, 2017-10-17)
ipcore_dir\create_e_mac.tcl (1284, 2015-11-19)
ipcore_dir\create_fifo_48_48_64.tcl (1274, 2015-08-27)
ipcore_dir\create_fifo_64_8_1024.tcl (1275, 2015-08-19)
ipcore_dir\create_fifo_8_8_2048.tcl (1274, 2015-08-21)
ipcore_dir\create_ram_16x32.tcl (1280, 2015-11-09)
ipcore_dir\create_ram_8x50.tcl (1279, 2015-11-09)
ipcore_dir\edit_fifo_64_8_1024.tcl (1130, 2015-08-21)
ipcore_dir\edit_fifo_8_8_2048.tcl (1129, 2015-09-16)
ipcore_dir\edit_ram_8x50.tcl (1124, 2017-10-17)
ipcore_dir\fifo_48_48_64 (0, 2015-11-20)
ipcore_dir\fifo_48_48_64.asy (889, 2015-08-27)
ipcore_dir\fifo_48_48_64.gise (1384, 2017-10-17)
ipcore_dir\fifo_48_48_64.ncf (0, 2015-11-26)
ipcore_dir\fifo_48_48_64.ngc (75898, 2015-08-27)
ipcore_dir\fifo_48_48_64.sym (2437, 2015-08-27)
ipcore_dir\fifo_48_48_64.v (14194, 2015-08-27)
ipcore_dir\fifo_48_48_64.veo (4561, 2015-08-27)
ipcore_dir\fifo_48_48_64.xco (7309, 2015-08-27)
ipcore_dir\fifo_48_48_64.xise (4933, 2015-08-28)
ipcore_dir\fifo_48_48_64\doc (0, 2015-11-20)
... ...
The following files were generated for 'icon_pro' in directory
D:\testcodes\fpga\ethernet_loopback_new_v1\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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