usb_rd_buffer
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：4308KB
下载次数：5
上传日期：2017-11-20 10:37:25
上 传 者：
marktuwen
说明： FPGA（SPARTAN6）通过USB协议与开发板上的USB芯片进行数据读写测试，在上位机上可以看到USB发来的数据，也可以通过修改VERILOG代码完成数据的接收
(FPGA (SPARTAN6) can read and write data through the USB chip on the development board through the USB protocol. The data sent by USB can be seen on the host computer, and the data can be received by modifying the VERILOG code)
文件列表:
usb_rd_buffer (0, 2017-11-20)
usb_rd_buffer\blk_ram.ngc (15774, 2012-11-07)
usb_rd_buffer\blk_ram.v (5807, 2012-11-07)
usb_rd_buffer\debug.cdc (20661, 2012-11-16)
usb_rd_buffer\iseconfig (0, 2015-10-29)
usb_rd_buffer\iseconfig\sys_clk.xreport (20552, 2012-11-12)
usb_rd_buffer\iseconfig\usb_20121107.projectmgr (6632, 2012-11-14)
usb_rd_buffer\iseconfig\usb_20121107_copy.projectmgr (4168, 2012-11-14)
usb_rd_buffer\iseconfig\usb_20121107_copy_rd_rd.projectmgr (5661, 2012-11-15)
usb_rd_buffer\iseconfig\usb_20121115_rd.projectmgr (6603, 2012-12-05)
usb_rd_buffer\iseconfig\usb_20121206.projectmgr (5808, 2013-03-11)
usb_rd_buffer\iseconfig\usb_inter.xreport (20626, 2017-11-20)
usb_rd_buffer\iseconfig\usb_rd_buffer.projectmgr (9525, 2015-10-28)
usb_rd_buffer\pll_200m_100m.v (7162, 2012-10-25)
usb_rd_buffer\sys_clk.v (791, 2012-11-12)
usb_rd_buffer\ucf.ucf (2717, 2012-12-08)
usb_rd_buffer\usage_statistics_webtalk.html (193251, 2013-03-11)
usb_rd_buffer\usb_inter.bgn (9086, 2015-10-27)
usb_rd_buffer\usb_inter.bit (5465086, 2015-10-27)
usb_rd_buffer\usb_inter.bld (3178, 2015-10-27)
usb_rd_buffer\usb_inter.cmd_log (16059, 2015-10-27)
usb_rd_buffer\usb_inter.drc (1131, 2015-10-27)
usb_rd_buffer\usb_inter.lso (6, 2015-10-27)
usb_rd_buffer\usb_inter.ncd (976613, 2015-10-27)
usb_rd_buffer\usb_inter.ngc (80209, 2015-10-27)
usb_rd_buffer\usb_inter.ngd (2531202, 2015-10-27)
usb_rd_buffer\usb_inter.ngr (72064, 2015-10-27)
usb_rd_buffer\usb_inter.pad (44609, 2015-10-27)
usb_rd_buffer\usb_inter.par (15212, 2015-10-27)
usb_rd_buffer\usb_inter.pcf (490664, 2015-10-27)
usb_rd_buffer\usb_inter.prj (140, 2015-10-27)
usb_rd_buffer\usb_inter.ptwx (20321, 2015-10-27)
usb_rd_buffer\usb_inter.stx (0, 2015-10-27)
usb_rd_buffer\usb_inter.syr (40182, 2015-10-27)
usb_rd_buffer\usb_inter.twr (154109, 2015-10-27)
usb_rd_buffer\usb_inter.twx (174576, 2015-10-27)
usb_rd_buffer\usb_inter.unroutes (305, 2015-10-27)
usb_rd_buffer\usb_inter.ut (737, 2015-10-27)
usb_rd_buffer\usb_inter.v (1665, 2015-10-22)
usb_rd_buffer\usb_inter.xpi (46, 2015-10-27)
... ...
The following files were generated for 'icon_pro' in directory
L:\DQQ_FPGA\virtex6vlx130t\USB3.0\usb_20121107\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：