fft-dit-fpga-master
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：26KB
下载次数：17
上传日期：2017-12-05 15:46:41
上 传 者：
slplion
说明： 快速傅里叶变换verilog代码。时域抽取
(the code of fft in verilog. DIT algorithm)
文件列表:
LICENSE.txt (1055, 2012-08-23)
butterfly.v (5872, 2012-08-23)
dit.v (22464, 2012-08-23)
dut_dit.v (704, 2012-08-23)
generate_twiddlefactors.py (1521, 2012-08-23)
myhdl.vpi (30078, 2012-08-23)
pyfft.py (1225, 2012-08-23)
qa_dit.py (7578, 2012-08-23)
twiddlefactors_N.v.t (718, 2012-08-23)
Decimation-In-Time Fast Fourier Transform
I've tried to make the implementation simple and well documented.
I have not tried to make it efficient.
dit.v - Contains main module.
buffer.v - Contains a module for a single butterfly step.
generate_twiddlefactors.py - Contains function to generate a verilog file with twiddlefactors.
twiddlefactors_N.v.t - Template used to generate verilog file.
dut_dit.v - A wrapper around the 'dit' module to allow verification with MyHDL.
qa_dit.py - A MyHDL test bench for verification.
Requires MyHDL, iverilog and numpy to be installed.
pyfft.py - Generates output of intermediate FFT stages. Useful for debugging.
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