urat接收程序
所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:2938KB
下载次数:2
上传日期:2017-12-15 14:17:49
上 传 者:
Thealeh
说明: uart串口接收程序,实现基于Rs232传输线的数据的接收。
(UART serial receiving program to realize data receiving based on Rs232 transmission line.)
文件列表:
class10\pro\uart_byte_rx\iseconfig\uart_byte_rx.projectmgr (9055, 2017-12-15)
class10\pro\uart_byte_rx\iseconfig\uart_byte_rx.xreport (20766, 2017-12-15)
class10\pro\uart_byte_rx\iseconfig\uart_byte_tx.xreport (20766, 2017-12-07)
class10\pro\uart_byte_rx\pa.fromHdl.tcl (671, 2017-12-11)
class10\pro\uart_byte_rx\par_usage_statistics.html (4139, 2017-12-08)
class10\pro\uart_byte_rx\planAhead_pid3388.debug (3790, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_1\planAhead.jou (546, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_1\planAhead.log (3712, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_1\planAhead_run.log (3059, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_2\uart_byte_rx.data\constrs_1\fileset.xml (539, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_2\uart_byte_rx.data\sim_1\fileset.xml (514, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_2\uart_byte_rx.data\sources_1\fileset.xml (588, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_2\uart_byte_rx.data\wt\project.wpc (105, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_2\uart_byte_rx.data\wt\webtalk_pa.xml (1335, 2017-12-11)
class10\pro\uart_byte_rx\planAhead_run_2\uart_byte_rx.ppr (1036, 2017-12-11)
class10\pro\uart_byte_rx\transcript (1849, 2017-12-15)
class10\pro\uart_byte_rx\uart.cdc (3182, 2017-12-12)
class10\pro\uart_byte_rx\uart.ucf (368, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.bgn (7844, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.bld (2556, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.cmd_log (4086, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.drc (787, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.gise (16255, 2017-12-15)
class10\pro\uart_byte_rx\uart_byte_rx.lso (6, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.ncd (209993, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.ngc (56019, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.ngd (516927, 2017-12-11)
class10\pro\uart_byte_rx\uart_byte_rx.ngr (134471, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.pad (14236, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.par (11523, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.pcf (52002, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.prj (41, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.ptwx (18998, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.stx (0, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.syr (20535, 2017-12-12)
class10\pro\uart_byte_rx\uart_byte_rx.twr (144211, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.twx (170511, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.unroutes (161, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.ut (556, 2017-12-08)
class10\pro\uart_byte_rx\uart_byte_rx.xise (37599, 2017-12-12)
... ...
The following files were generated for 'icon_pro' in directory
D:\FPGA\class\class10\pro\uart_byte_rx\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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