source
所属分类：其他
开发工具：Verilog
文件大小：31841KB
下载次数：1
上传日期：2017-12-19 11:37:21
上 传 者：
YUY-E
说明： 编程verilog 适用于FPGA开发 适合初学者 极好极好极好
(verilog hdl fpga eg01)
文件列表:
lab1\counter.v (1114, 2017-07-18)
lab1\flash_led_ctl.v (1078, 2017-07-18)
lab1\flash_led_top.v (920, 2017-07-18)
lab1\sim\Flash_led_top_tb.v (1006, 2017-07-18)
lab1\xdc\flash_led_top.xdc (1477, 2017-07-18)
lab2\count_down.v (2209, 2016-10-24)
lab2\push_detect.v (1204, 2016-10-24)
lab2\show_who.v (1240, 2016-10-24)
lab2\sim\Smart_responder_tb.v (821, 2017-01-05)
lab2\Smart_responder.v (1096, 2017-01-05)
lab2\Smart_responder.xdc (1442, 2016-10-24)
lab3\dive_clk.v (1589, 2016-11-15)
lab3\divo_clk.v (2915, 2016-11-15)
lab3\div_clk.v (1353, 2017-07-11)
lab3\sim\sim_div.v (398, 2016-11-15)
lab3\xdc\IO.xdc (1379, 2016-11-15)
lab4\coe\filter_data.coe (4464, 2016-11-15)
lab4\FIR_count.v (303, 2016-11-15)
lab4\FIR_filter.v (1784, 2016-11-15)
lab4\FIR_top.v (411, 2016-11-15)
lab4\Matlab\mylowerfilter.m (629, 2016-11-15)
lab4\Matlab\result.m (151, 2016-11-15)
lab4\Matlab\signal.m (325, 2016-11-15)
lab4\multip.v (940, 2016-11-15)
lab4\sim\FIR_tb.v (252, 2016-11-15)
lab5\APP\serial_port_utility_latest.exe (7447240, 2016-05-18)
lab5\btn_debounce.v (791, 2016-11-15)
lab5\code_ctl.v (1313, 2016-11-15)
lab5\data_show.v (1169, 2016-11-15)
lab5\delay_10ms.v (939, 2016-11-15)
lab5\H2L_detect.v (326, 2016-11-15)
lab5\input_signal_processing.v (1424, 2016-11-15)
lab5\L2H_detect.v (326, 2016-11-15)
lab5\meta_harden.v (405, 2016-11-15)
lab5\number_encode.v (1918, 2016-11-15)
lab5\out_ctl.v (304, 2016-11-15)
lab5\reverse_detect.v (345, 2016-11-15)
lab5\rx_band_gen.v (883, 2016-11-15)
lab5\rx_ctl.v (2082, 2016-11-15)
lab5\rx_top.v (762, 2016-11-15)
... ...
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