1496993155583-osenlogic264decoder
所属分类：其他
开发工具：Verilog
文件大小：8209KB
下载次数：5
上传日期：2017-12-28 14:37:58
上 传 者：
boboxiao
说明： 完成了264编码器的编码功能，在modelsim上仿真，可以通过
(The encoding function of the 264 encoder is completed, which is simulated on the Modelsim and can be passed through)
文件列表:
OSenLogic264decoder (0, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df (0, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\display (0, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\display\display_mem_reader.sv (12712, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\display\dp_ram_display.v (478, 2017-03-27)
OSenLogic264decoder\OSD10_rtl_no_df\display\sync_ram_display.v (718, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\display\video_ctrl.v (3770, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\display\video_output.v (3491, 2017-06-06)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core (0, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\bitstream_controller.v (7567, 2017-05-23)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\bitstream_ena_gen.v (2006, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_fsm.v (5421, 2016-09-30)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_len_gen.v (4039, 2017-04-20)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_read_levels.v (12059, 2016-09-30)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_read_run_befores.v (10185, 2017-04-20)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_read_total_coeffs.v (31538, 2013-09-26)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_read_total_zeros.v (18177, 2017-04-20)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\cavlc_top.v (8361, 2016-09-30)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\dc_fifo.v (3264, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\dc_fifo_async_read.v (2086, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\debug_stuff.v (2446, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\decode_stream.v (39825, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\defines.v (13280, 2017-04-19)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\dp_ram.v (930, 2017-05-11)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\dp_ram_be.v (933, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\ext_mem_writer.v (14849, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\get_mvp.v (25046, 2017-04-23)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\inter_pred_calc.v (75513, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\inter_pred_fsm.v (9515, 2017-04-21)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\inter_pred_load.sv (63712, 2017-05-23)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\inter_pred_top.v (18098, 2017-06-09)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\intra4x4_pred_mode_decoding.v (4993, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\intra_pred_calc.v (27953, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\intra_pred_fsm.v (12827, 2017-04-21)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\intra_pred_regs.v (32146, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\intra_pred_top.v (7278, 2017-04-21)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\nC_decoding.v (7733, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\pps.v (9454, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\ram.v (1030, 2017-04-17)
OSenLogic264decoder\OSD10_rtl_no_df\ip_core\rbsp_buffer.v (7352, 2017-05-23)
... ...
1.Files
OSD10_rtl_no_df is source folder of 2*** decoder, no deblocking filter verison,
for verison with deblocking filter, please contact author(eebq, qq:1517***2772)
OSD10_testbench is testbench folder of 2*** decoder.
software is ralated software:1.C Model 2.pli_fputc 3.hex2bin_new
2. how to simulate
1.in modelsim, create a project.
2.add all files in 3 directories:
"OSD10_testbench", "OSD10_rtl_no_df/display", "OSD10_rtl_no_df/ip_core"
3.complile all files,
4.there are two modes of simulation output , one is binary mode and the other is
ascii mode, the default mode is binary mode.
1.binary output mode:
in modelsim console window, type
"vsim -vopt -pli pli_fputc***.dll work.bitstream_tb".
pli_fputc***.dll is a pli library I write for dump binary out.yuv file, it runs
in windows ***bit,
if you are using windows 32 bit, instead it with fputc32.dll.
the source of pli_fputc is in software/pli_fputc_src directory.
2.ascii output mode:
you can simulate without pli_fputc.dll, it simulate much
faster using command "vsim -vopt work.bitstream_tb".
to do this, you should modify Line 378 to
"ext_ram_32 #(.BinMode(0)) ext_ram_32".
In this mode, you must convert ascii file "out.yuv" to binary
mode with hex2bin_new.exe.
the source of hex2bin_new is in software/hex2bin_new_src directory.
3. C model
1.About C model
-- A simple C model is provided to compare the output of HDL and software,
--C model is in software/c_model/src/
-- The C model is tested, the output yuv file is same with JM86.
-- by default the deblocking filter is turned off, to open it,just
uncomment line 363:"deblocking_filter(slice_header, pps);"
2.how to build and run
1.cd to this directory.
2.type "make" to build bitstream.exe, gcc is required to build it.
3.run bitstream.exe to decode the "in.2***" file in the same directory.
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