CoreSPI_21_eval
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：614KB
下载次数：29
上传日期：2011-05-03 09:54:48
上 传 者：
ren0feng
说明： SPI IP核源码，包括Verilog和VHDL两种语言源码
(SPI IP core source code, including the two languages Verilog and VHDL source code)
文件列表:
CoreSPI_eval (0, 2005-02-04)
CoreSPI_eval\doc (0, 2005-01-22)
CoreSPI_eval\doc\CHANGES.txt (306, 2005-01-24)
CoreSPI_eval\doc\CoreSPI_DS.pdf (121189, 2004-08-06)
CoreSPI_eval\doc\CoreSPI_RN.pdf (55208, 2005-01-21)
CoreSPI_eval\doc\CoreSPI_UG.pdf (199603, 2004-03-18)
CoreSPI_eval\sim (0, 2005-01-22)
CoreSPI_eval\sim\mti_full (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\_info (3035, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_master (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_master\_primary.dat (678, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_master\behv.dat (4843, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_master\behv.asm (22360, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_slave (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_slave\_primary.dat (609, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_slave\behv.dat (2143, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\spi_slave\behv.asm (12040, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\corespi (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\corespi\_primary.dat (746, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\corespi\behv.dat (5746, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\corespi\behv.asm (40224, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\tb_vhdl (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\tb_vhdl\_primary.dat (357, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\tb_vhdl\behv.dat (8176, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vhdl\tb_vhdl\behv.asm (56854, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib\_info (1216, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib\corespi_pkg (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib\corespi_pkg\_primary.dat (2892, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib\corespi_pkg\_vhdl.asm (2288, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib\corespi_pkg\body.dat (16014, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\corespi_lib\corespi_pkg\body.asm (92496, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vlog (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vlog\_info (769, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vlog\spi_master (0, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vlog\spi_master\verilog.asm (35280, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vlog\spi_master\_primary.dat (7244, 2005-02-04)
CoreSPI_eval\sim\mti_full\user\work_vlog\spi_slave (0, 2005-02-04)
... ...
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