xapp1065
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:19KB
下载次数:1
上传日期:2018-01-03 22:45:43
上 传 者:
denisys
说明: Xilinx xapp 1065 application note
文件列表:
rtl\DCM_CLKGEN_SOFTSPREAD.v (5687, 2009-11-18)
rtl\DCM_CLKGEN_SOFTSPREAD_M7D4.v (6146, 2009-11-18)
rtl\SSCONTROL.v (6717, 2009-11-18)
rtl\SSTOP.v (8456, 2009-11-18)
rtl\XAPP_SS.v (8547, 2009-11-18)
rtl\XAPP_SS_M7D4.v (8578, 2009-11-18)
rtl (0, 2010-03-01)
simulation\TESTBENCH.v (2261, 2010-03-01)
simulation (0, 2010-03-01)
**************************************************************************************************************
** Copyright 2010 Xilinx, Inc. All rights reserved.
** This file contains confidential and proprietary information of Xilinx, Inc. and
** is protected under U.S. and international copyright and other intellectual property laws.
**************************************************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/
** \ \ readme.txt Version: 1.0
** / / Date Last Modified: 3/19/10
** /___/ /\ Date Created: 3/19/10
** \ \ / \ Associated Filename: xapp1065.zip
** \___\/\___\
**
** Device: Spartan-6
** Purpose: Soft spread spectrum generation using DCM_CLKGEN
** Reference:
** Revision History:
**
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**
** Disclaimer:
**
** This disclaimer is not a license and does not grant any rights to the materials
** distributed herewith. Except as otherwise provided in a valid license issued to you
** by Xilinx, and to the maximum extent permitted by applicable law:
** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
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** Critical Applications:
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** Xilinx products are not designed or intended to be fail-safe, or for use in any application
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This readme describes how to use the files that come with , e.g., XAPP1065
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This archive inlcudes the following set of design files:
HDL Files
===========
- XAPP_SS.v - Top level example design file demonstrating video setup (7/2 clock mulitplication)
- DCM_CLKGEN_SOFTSPREAD.v - Wrapper combining DCM_CLKGEN with SOFT Spread Spectrum state machines
- SSTOP.v - SOFT Spread Spectrum state machine
- SSCONTROL.v - Programming interface used to reprogram DCM_CLKGEN
- XAPP_SS_M7D4.v - Top level design fie showing how to modify for 7/4 clock multiplication
- DCM_CLKGEN_SOFTSPREAD_M7D4.v - Wrapper modified for 7/4 clock multiplication
- TESTBENCH.v - Example testbench for simulating. Simulation supported in 12.1
This design takes a fixed frequency differential clock and generates a spread spectrum clock using the
soft mode of DCM_CLKGEN. Several outputs are provided for measuring.
The design replaces a typical component instantiation of DCM_CLKGEN with DCM_CLKGEN_SOFTSPREAD.v.
DCM_CLKGEN_SOFTSPREAD connects the DCM_CLKGEN primtive to the state machine required for the soft
spread spectrum generation, SSTOP.v.
Simulation Files
===========
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