xapp1065

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:19KB
下载次数:1
上传日期:2018-01-03 22:45:43
上 传 者denisys
说明:  Xilinx xapp 1065 application note

文件列表:
rtl\DCM_CLKGEN_SOFTSPREAD.v (5687, 2009-11-18)
rtl\DCM_CLKGEN_SOFTSPREAD_M7D4.v (6146, 2009-11-18)
rtl\SSCONTROL.v (6717, 2009-11-18)
rtl\SSTOP.v (8456, 2009-11-18)
rtl\XAPP_SS.v (8547, 2009-11-18)
rtl\XAPP_SS_M7D4.v (8578, 2009-11-18)
rtl (0, 2010-03-01)
simulation\TESTBENCH.v (2261, 2010-03-01)
simulation (0, 2010-03-01)

************************************************************************************************************** ** Copyright 2010 Xilinx, Inc. All rights reserved. ** This file contains confidential and proprietary information of Xilinx, Inc. and ** is protected under U.S. and international copyright and other intellectual property laws. ************************************************************************************************************** ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ ** \ \ readme.txt Version: 1.0 ** / / Date Last Modified: 3/19/10 ** /___/ /\ Date Created: 3/19/10 ** \ \ / \ Associated Filename: xapp1065.zip ** \___\/\___\ ** ** Device: Spartan-6 ** Purpose: Soft spread spectrum generation using DCM_CLKGEN ** Reference: ** Revision History: ** ************************************************************************************************************** ** ** Disclaimer: ** ** This disclaimer is not a license and does not grant any rights to the materials ** distributed herewith. Except as otherwise provided in a valid license issued to you ** by Xilinx, and to the maximum extent permitted by applicable law: ** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, ** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, ** INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR ** FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract ** or tort, including negligence, or under any other theory of liability) for any loss or damage ** of any kind or nature related to, arising under or in connection with these materials, ** including for any direct, or any indirect, special, incidental, or consequential loss ** or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered ** as a result of any action brought by a third party) even if such damage or loss was ** reasonably foreseeable or Xilinx had been advised of the possibility of the same. ** ** ** Critical Applications: ** ** Xilinx products are not designed or intended to be fail-safe, or for use in any application ** requiring fail-safe performance, such as life-support or safety devices or systems, ** Class III medical devices, nuclear facilities, applications related to the deployment of airbags, ** or any other applications that could lead to death, personal injury, or severe property or ** environmental damage (individually and collectively, "Critical Applications"). Customer assumes ** the sole risk and liability of any use of Xilinx products in Critical Applications, subject only ** to applicable laws and regulations governing limitations on product liability. ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************************************************** This readme describes how to use the files that come with , e.g., XAPP1065 ************************************************************************************************************** This archive inlcudes the following set of design files: HDL Files =========== - XAPP_SS.v - Top level example design file demonstrating video setup (7/2 clock mulitplication) - DCM_CLKGEN_SOFTSPREAD.v - Wrapper combining DCM_CLKGEN with SOFT Spread Spectrum state machines - SSTOP.v - SOFT Spread Spectrum state machine - SSCONTROL.v - Programming interface used to reprogram DCM_CLKGEN - XAPP_SS_M7D4.v - Top level design fie showing how to modify for 7/4 clock multiplication - DCM_CLKGEN_SOFTSPREAD_M7D4.v - Wrapper modified for 7/4 clock multiplication - TESTBENCH.v - Example testbench for simulating. Simulation supported in 12.1 This design takes a fixed frequency differential clock and generates a spread spectrum clock using the soft mode of DCM_CLKGEN. Several outputs are provided for measuring. The design replaces a typical component instantiation of DCM_CLKGEN with DCM_CLKGEN_SOFTSPREAD.v. DCM_CLKGEN_SOFTSPREAD connects the DCM_CLKGEN primtive to the state machine required for the soft spread spectrum generation, SSTOP.v. Simulation Files =========== **************************************************************************************************************

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