Design
所属分类：其他
开发工具：Verilog
文件大小：2949KB
下载次数：4
上传日期：2018-01-07 09:04:01
上 传 者：
jiangnan34dp
说明： 利用Xilinx ISE用Verilog编写的计算器
(Using Xilinx ISEalculator and register heap program written in Verilog HDL language)
文件列表:
Design\adder_sch.vf (1678, 2017-11-24)
Design\AddSup1b_drc.vf (1398, 2017-11-30)
Design\AddSup4b_drc.vf (2732, 2018-01-02)
Design\AddSup4b_isim_beh.exe (94720, 2018-01-01)
Design\AddSup4b_stx_beh.prj (267, 2018-01-02)
Design\AddSup4b_summary.html (3687, 2018-01-02)
Design\AddSup8b_isim_beh.exe (94720, 2018-01-02)
Design\clkdiv.v (702, 2017-11-20)
Design\design.bgn (8142, 2018-01-06)
Design\design.bit (6692664, 2018-01-06)
Design\Design.bld (1001, 2018-01-06)
Design\Design.cmd_log (6433, 2018-01-06)
Design\design.drc (190, 2018-01-06)
Design\Design.gise (20731, 2018-01-06)
Design\Design.lso (6, 2018-01-06)
Design\Design.ncd (43986, 2018-01-06)
Design\Design.ngc (44414, 2018-01-06)
Design\Design.ngd (68098, 2018-01-06)
Design\Design.ngr (49015, 2018-01-06)
Design\Design.pad (28956, 2018-01-06)
Design\Design.par (8692, 2018-01-06)
Design\Design.pcf (1325, 2018-01-06)
Design\Design.prj (171, 2018-01-06)
Design\Design.ptwx (17233, 2018-01-06)
Design\Design.stx (0, 2018-01-06)
Design\Design.syr (24168, 2018-01-06)
Design\Design.twr (5095, 2018-01-06)
Design\Design.twx (23189, 2018-01-06)
Design\Design.unroutes (161, 2018-01-06)
Design\Design.ut (742, 2018-01-06)
Design\Design.v (2568, 2018-01-05)
Design\Design.xise (38175, 2018-01-05)
Design\Design.xpi (46, 2018-01-06)
Design\Design.xst (1068, 2018-01-06)
Design\Design_bitgen.xwbt (197, 2018-01-06)
Design\Design_envsettings.html (10792, 2018-01-06)
Design\Design_guide.ncd (43986, 2018-01-06)
Design\Design_isim_beh.exe (94720, 2018-01-02)
Design\Design_map.map (7353, 2018-01-06)
Design\Design_map.mrp (16150, 2018-01-06)
... ...
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